Lines Matching full:vdev
87 static void ivpu_hw_read_platform(struct ivpu_device *vdev) in ivpu_hw_read_platform() argument
93 vdev->platform = platform; in ivpu_hw_read_platform()
95 vdev->platform = IVPU_PLATFORM_SILICON; in ivpu_hw_read_platform()
97 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in ivpu_hw_read_platform()
98 ivpu_platform_to_str(vdev->platform), vdev->platform); in ivpu_hw_read_platform()
101 static void ivpu_hw_wa_init(struct ivpu_device *vdev) in ivpu_hw_wa_init() argument
103 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); in ivpu_hw_wa_init()
104 vdev->wa.clear_runtime_mem = false; in ivpu_hw_wa_init()
105 vdev->wa.d3hot_after_power_off = true; in ivpu_hw_wa_init()
110 vdev->wa.interrupt_clear_with_0 = true; in ivpu_hw_wa_init()
120 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev) in ivpu_hw_timeouts_init() argument
122 if (ivpu_is_simics(vdev) || ivpu_is_fpga(vdev)) { in ivpu_hw_timeouts_init()
123 vdev->timeout.boot = 100000; in ivpu_hw_timeouts_init()
124 vdev->timeout.jsm = 50000; in ivpu_hw_timeouts_init()
125 vdev->timeout.tdr = 2000000; in ivpu_hw_timeouts_init()
126 vdev->timeout.reschedule_suspend = 1000; in ivpu_hw_timeouts_init()
128 vdev->timeout.boot = 1000; in ivpu_hw_timeouts_init()
129 vdev->timeout.jsm = 500; in ivpu_hw_timeouts_init()
130 vdev->timeout.tdr = 2000; in ivpu_hw_timeouts_init()
131 vdev->timeout.reschedule_suspend = 10; in ivpu_hw_timeouts_init()
135 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev) in ivpu_pll_wait_for_cmd_send() argument
141 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio, in ivpu_pll_cmd_send() argument
147 ret = ivpu_pll_wait_for_cmd_send(vdev); in ivpu_pll_cmd_send()
149 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret); in ivpu_pll_cmd_send()
171 ret = ivpu_pll_wait_for_cmd_send(vdev); in ivpu_pll_cmd_send()
173 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret); in ivpu_pll_cmd_send()
178 static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable) in ivpu_pll_wait_for_lock() argument
188 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev) in ivpu_pll_wait_for_status_ready() argument
196 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) in ivpu_pll_init_frequency_ratios() argument
198 struct ivpu_hw_info *hw = vdev->hw; in ivpu_pll_init_frequency_ratios()
214 static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev) in ivpu_hw_37xx_wait_for_vpuip_bar() argument
219 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) in ivpu_pll_drive() argument
221 struct ivpu_hw_info *hw = vdev->hw; in ivpu_pll_drive()
227 ivpu_dbg(vdev, PM, "Skipping PLL request on %s\n", in ivpu_pll_drive()
228 ivpu_platform_to_str(vdev->platform)); in ivpu_pll_drive()
240 ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n", in ivpu_pll_drive()
243 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config); in ivpu_pll_drive()
245 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret); in ivpu_pll_drive()
249 ret = ivpu_pll_wait_for_lock(vdev, enable); in ivpu_pll_drive()
251 ivpu_err(vdev, "Timed out waiting for PLL lock\n"); in ivpu_pll_drive()
256 ret = ivpu_pll_wait_for_status_ready(vdev); in ivpu_pll_drive()
258 ivpu_err(vdev, "Timed out waiting for PLL ready status\n"); in ivpu_pll_drive()
262 ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev); in ivpu_pll_drive()
264 ivpu_err(vdev, "Timed out waiting for VPUIP bar\n"); in ivpu_pll_drive()
272 static int ivpu_pll_enable(struct ivpu_device *vdev) in ivpu_pll_enable() argument
274 return ivpu_pll_drive(vdev, true); in ivpu_pll_enable()
277 static int ivpu_pll_disable(struct ivpu_device *vdev) in ivpu_pll_disable() argument
279 return ivpu_pll_drive(vdev, false); in ivpu_pll_disable()
282 static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev) in ivpu_boot_host_ss_rst_clr_assert() argument
293 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_rst_drive() argument
310 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_clk_drive() argument
327 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qreqn_check() argument
337 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qacceptn_check() argument
347 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qdeny_check() argument
357 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qrenqn_check() argument
368 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qacceptn_check() argument
379 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qdeny_check() argument
390 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev) in ivpu_boot_host_ss_configure() argument
392 ivpu_boot_host_ss_rst_clr_assert(vdev); in ivpu_boot_host_ss_configure()
394 return ivpu_boot_noc_qreqn_check(vdev, 0x0); in ivpu_boot_host_ss_configure()
397 static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev) in ivpu_boot_vpu_idle_gen_disable() argument
402 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_axi_drive() argument
414 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); in ivpu_boot_host_ss_axi_drive()
416 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); in ivpu_boot_host_ss_axi_drive()
420 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0); in ivpu_boot_host_ss_axi_drive()
422 ivpu_err(vdev, "Failed qdeny check: %d\n", ret); in ivpu_boot_host_ss_axi_drive()
427 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev) in ivpu_boot_host_ss_axi_enable() argument
429 return ivpu_boot_host_ss_axi_drive(vdev, true); in ivpu_boot_host_ss_axi_enable()
432 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_top_noc_drive() argument
447 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); in ivpu_boot_host_ss_top_noc_drive()
449 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); in ivpu_boot_host_ss_top_noc_drive()
453 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0); in ivpu_boot_host_ss_top_noc_drive()
455 ivpu_err(vdev, "Failed qdeny check: %d\n", ret); in ivpu_boot_host_ss_top_noc_drive()
460 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev) in ivpu_boot_host_ss_top_noc_enable() argument
462 return ivpu_boot_host_ss_top_noc_drive(vdev, true); in ivpu_boot_host_ss_top_noc_enable()
465 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_trickle_drive() argument
477 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_drive() argument
489 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_wait_for_pwr_island_status() argument
492 if (ivpu_is_fpga(vdev)) in ivpu_boot_wait_for_pwr_island_status()
499 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_isolation_drive() argument
511 static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_dpu_active_drive() argument
523 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev) in ivpu_boot_pwr_domain_enable() argument
527 ivpu_boot_pwr_island_trickle_drive(vdev, true); in ivpu_boot_pwr_domain_enable()
528 ivpu_boot_pwr_island_drive(vdev, true); in ivpu_boot_pwr_domain_enable()
530 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1); in ivpu_boot_pwr_domain_enable()
532 ivpu_err(vdev, "Timed out waiting for power island status\n"); in ivpu_boot_pwr_domain_enable()
536 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0); in ivpu_boot_pwr_domain_enable()
538 ivpu_err(vdev, "Failed qrenqn check %d\n", ret); in ivpu_boot_pwr_domain_enable()
542 ivpu_boot_host_ss_clk_drive(vdev, true); in ivpu_boot_pwr_domain_enable()
543 ivpu_boot_pwr_island_isolation_drive(vdev, false); in ivpu_boot_pwr_domain_enable()
544 ivpu_boot_host_ss_rst_drive(vdev, true); in ivpu_boot_pwr_domain_enable()
545 ivpu_boot_dpu_active_drive(vdev, true); in ivpu_boot_pwr_domain_enable()
550 static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev) in ivpu_boot_pwr_domain_disable() argument
552 ivpu_boot_dpu_active_drive(vdev, false); in ivpu_boot_pwr_domain_disable()
553 ivpu_boot_pwr_island_isolation_drive(vdev, true); in ivpu_boot_pwr_domain_disable()
554 ivpu_boot_pwr_island_trickle_drive(vdev, false); in ivpu_boot_pwr_domain_disable()
555 ivpu_boot_pwr_island_drive(vdev, false); in ivpu_boot_pwr_domain_disable()
557 return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0); in ivpu_boot_pwr_domain_disable()
560 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev) in ivpu_boot_no_snoop_enable() argument
571 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev) in ivpu_boot_tbu_mmu_enable() argument
583 static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev) in ivpu_boot_soc_cpu_boot() argument
599 val = vdev->fw->entry_point >> 9; in ivpu_boot_soc_cpu_boot()
605 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in ivpu_boot_soc_cpu_boot()
606 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); in ivpu_boot_soc_cpu_boot()
609 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_d0i3_drive() argument
616 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); in ivpu_boot_d0i3_drive()
629 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); in ivpu_boot_d0i3_drive()
634 static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev) in ivpu_hw_37xx_info_init() argument
636 struct ivpu_hw_info *hw = vdev->hw; in ivpu_hw_37xx_info_init()
642 ivpu_pll_init_frequency_ratios(vdev); in ivpu_hw_37xx_info_init()
649 ivpu_hw_read_platform(vdev); in ivpu_hw_37xx_info_init()
650 ivpu_hw_wa_init(vdev); in ivpu_hw_37xx_info_init()
651 ivpu_hw_timeouts_init(vdev); in ivpu_hw_37xx_info_init()
656 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) in ivpu_hw_37xx_reset() argument
660 if (ivpu_boot_pwr_domain_disable(vdev)) { in ivpu_hw_37xx_reset()
661 ivpu_err(vdev, "Failed to disable power domain\n"); in ivpu_hw_37xx_reset()
665 if (ivpu_pll_disable(vdev)) { in ivpu_hw_37xx_reset()
666 ivpu_err(vdev, "Failed to disable PLL\n"); in ivpu_hw_37xx_reset()
673 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev) in ivpu_hw_37xx_d0i3_enable() argument
677 ret = ivpu_boot_d0i3_drive(vdev, true); in ivpu_hw_37xx_d0i3_enable()
679 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); in ivpu_hw_37xx_d0i3_enable()
686 static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_d0i3_disable() argument
690 ret = ivpu_boot_d0i3_drive(vdev, false); in ivpu_hw_37xx_d0i3_disable()
692 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret); in ivpu_hw_37xx_d0i3_disable()
697 static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev) in ivpu_hw_37xx_power_up() argument
701 ret = ivpu_hw_37xx_d0i3_disable(vdev); in ivpu_hw_37xx_power_up()
703 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); in ivpu_hw_37xx_power_up()
705 ret = ivpu_pll_enable(vdev); in ivpu_hw_37xx_power_up()
707 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret); in ivpu_hw_37xx_power_up()
711 ret = ivpu_boot_host_ss_configure(vdev); in ivpu_hw_37xx_power_up()
713 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); in ivpu_hw_37xx_power_up()
722 ivpu_boot_vpu_idle_gen_disable(vdev); in ivpu_hw_37xx_power_up()
724 ret = ivpu_boot_pwr_domain_enable(vdev); in ivpu_hw_37xx_power_up()
726 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); in ivpu_hw_37xx_power_up()
730 ret = ivpu_boot_host_ss_axi_enable(vdev); in ivpu_hw_37xx_power_up()
732 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); in ivpu_hw_37xx_power_up()
736 ret = ivpu_boot_host_ss_top_noc_enable(vdev); in ivpu_hw_37xx_power_up()
738 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); in ivpu_hw_37xx_power_up()
743 static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev) in ivpu_hw_37xx_boot_fw() argument
745 ivpu_boot_no_snoop_enable(vdev); in ivpu_hw_37xx_boot_fw()
746 ivpu_boot_tbu_mmu_enable(vdev); in ivpu_hw_37xx_boot_fw()
747 ivpu_boot_soc_cpu_boot(vdev); in ivpu_hw_37xx_boot_fw()
752 static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev) in ivpu_hw_37xx_is_idle() argument
764 static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev) in ivpu_hw_37xx_power_down() argument
768 if (!ivpu_hw_37xx_is_idle(vdev)) in ivpu_hw_37xx_power_down()
769 ivpu_warn(vdev, "VPU not idle during power down\n"); in ivpu_hw_37xx_power_down()
771 if (ivpu_hw_37xx_reset(vdev)) { in ivpu_hw_37xx_power_down()
772 ivpu_err(vdev, "Failed to reset VPU\n"); in ivpu_hw_37xx_power_down()
776 if (ivpu_hw_37xx_d0i3_enable(vdev)) { in ivpu_hw_37xx_power_down()
777 ivpu_err(vdev, "Failed to enter D0I3\n"); in ivpu_hw_37xx_power_down()
784 static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_wdt_disable() argument
816 static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_pll_freq_get() argument
823 if (!ivpu_is_silicon(vdev)) in ivpu_hw_37xx_reg_pll_freq_get()
826 return ivpu_hw_37xx_pll_to_freq(pll_curr_ratio, vdev->hw->config); in ivpu_hw_37xx_reg_pll_freq_get()
829 static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_offset_get() argument
834 static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_size_get() argument
839 static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_enable_get() argument
844 static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id) in ivpu_hw_37xx_reg_db_set() argument
852 static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_ipc_rx_addr_get() argument
857 static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_ipc_rx_count_get() argument
864 static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) in ivpu_hw_37xx_reg_ipc_tx_set() argument
869 static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_clear() argument
874 static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_enable() argument
882 static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_disable() argument
890 static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_wdt_nce_handler() argument
892 ivpu_err_ratelimited(vdev, "WDT NCE irq\n"); in ivpu_hw_37xx_irq_wdt_nce_handler()
894 ivpu_pm_schedule_recovery(vdev); in ivpu_hw_37xx_irq_wdt_nce_handler()
897 static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_wdt_mss_handler() argument
899 ivpu_err_ratelimited(vdev, "WDT MSS irq\n"); in ivpu_hw_37xx_irq_wdt_mss_handler()
901 ivpu_hw_wdt_disable(vdev); in ivpu_hw_37xx_irq_wdt_mss_handler()
902 ivpu_pm_schedule_recovery(vdev); in ivpu_hw_37xx_irq_wdt_mss_handler()
905 static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_noc_firewall_handler() argument
907 ivpu_err_ratelimited(vdev, "NOC Firewall irq\n"); in ivpu_hw_37xx_irq_noc_firewall_handler()
909 ivpu_pm_schedule_recovery(vdev); in ivpu_hw_37xx_irq_noc_firewall_handler()
913 static u32 ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq) in ivpu_hw_37xx_irqv_handler() argument
920 ivpu_mmu_irq_evtq_handler(vdev); in ivpu_hw_37xx_irqv_handler()
923 ivpu_ipc_irq_handler(vdev); in ivpu_hw_37xx_irqv_handler()
926 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_37xx_irqv_handler()
929 ivpu_mmu_irq_gerr_handler(vdev); in ivpu_hw_37xx_irqv_handler()
932 ivpu_hw_37xx_irq_wdt_mss_handler(vdev); in ivpu_hw_37xx_irqv_handler()
935 ivpu_hw_37xx_irq_wdt_nce_handler(vdev); in ivpu_hw_37xx_irqv_handler()
938 ivpu_hw_37xx_irq_noc_firewall_handler(vdev); in ivpu_hw_37xx_irqv_handler()
944 static u32 ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq) in ivpu_hw_37xx_irqb_handler() argument
953 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", in ivpu_hw_37xx_irqb_handler()
957 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); in ivpu_hw_37xx_irqb_handler()
965 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", in ivpu_hw_37xx_irqb_handler()
984 ivpu_pm_schedule_recovery(vdev); in ivpu_hw_37xx_irqb_handler()
991 struct ivpu_device *vdev = ptr; in ivpu_hw_37xx_irq_handler() local
996 ret_irqv = ivpu_hw_37xx_irqv_handler(vdev, irq); in ivpu_hw_37xx_irq_handler()
997 ret_irqb = ivpu_hw_37xx_irqb_handler(vdev, irq); in ivpu_hw_37xx_irq_handler()
1005 static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev) in ivpu_hw_37xx_diagnose_failure() argument
1010 if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev)) in ivpu_hw_37xx_diagnose_failure()
1011 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); in ivpu_hw_37xx_diagnose_failure()
1014 ivpu_err(vdev, "WDT MSS timeout detected\n"); in ivpu_hw_37xx_diagnose_failure()
1017 ivpu_err(vdev, "WDT NCE timeout detected\n"); in ivpu_hw_37xx_diagnose_failure()
1020 ivpu_err(vdev, "NOC Firewall irq detected\n"); in ivpu_hw_37xx_diagnose_failure()
1023 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); in ivpu_hw_37xx_diagnose_failure()
1028 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", in ivpu_hw_37xx_diagnose_failure()