Lines Matching +full:static +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
63 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
73 static char *ivpu_platform_to_str(u32 platform) in ivpu_platform_to_str()
87 static void ivpu_hw_read_platform(struct ivpu_device *vdev) in ivpu_hw_read_platform()
93 vdev->platform = platform; in ivpu_hw_read_platform()
95 vdev->platform = IVPU_PLATFORM_SILICON; in ivpu_hw_read_platform()
98 ivpu_platform_to_str(vdev->platform), vdev->platform); in ivpu_hw_read_platform()
101 static void ivpu_hw_wa_init(struct ivpu_device *vdev) in ivpu_hw_wa_init()
103 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); in ivpu_hw_wa_init()
104 vdev->wa.clear_runtime_mem = false; in ivpu_hw_wa_init()
105 vdev->wa.d3hot_after_power_off = true; in ivpu_hw_wa_init()
110 vdev->wa.interrupt_clear_with_0 = true; in ivpu_hw_wa_init()
120 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev) in ivpu_hw_timeouts_init()
123 vdev->timeout.boot = 100000; in ivpu_hw_timeouts_init()
124 vdev->timeout.jsm = 50000; in ivpu_hw_timeouts_init()
125 vdev->timeout.tdr = 2000000; in ivpu_hw_timeouts_init()
126 vdev->timeout.reschedule_suspend = 1000; in ivpu_hw_timeouts_init()
128 vdev->timeout.boot = 1000; in ivpu_hw_timeouts_init()
129 vdev->timeout.jsm = 500; in ivpu_hw_timeouts_init()
130 vdev->timeout.tdr = 2000; in ivpu_hw_timeouts_init()
131 vdev->timeout.reschedule_suspend = 10; in ivpu_hw_timeouts_init()
135 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev) in ivpu_pll_wait_for_cmd_send()
141 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio, in ivpu_pll_cmd_send()
178 static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable) in ivpu_pll_wait_for_lock() argument
180 u32 exp_val = enable ? 0x1 : 0x0; in ivpu_pll_wait_for_lock()
188 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev) in ivpu_pll_wait_for_status_ready()
196 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) in ivpu_pll_init_frequency_ratios()
198 struct ivpu_hw_info *hw = vdev->hw; in ivpu_pll_init_frequency_ratios()
209 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio); in ivpu_pll_init_frequency_ratios()
210 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio); in ivpu_pll_init_frequency_ratios()
211 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); in ivpu_pll_init_frequency_ratios()
214 static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev) in ivpu_hw_37xx_wait_for_vpuip_bar()
219 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) in ivpu_pll_drive() argument
221 struct ivpu_hw_info *hw = vdev->hw; in ivpu_pll_drive()
228 ivpu_platform_to_str(vdev->platform)); in ivpu_pll_drive()
232 if (enable) { in ivpu_pll_drive()
233 target_ratio = hw->pll.pn_ratio; in ivpu_pll_drive()
234 config = hw->config; in ivpu_pll_drive()
243 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config); in ivpu_pll_drive()
249 ret = ivpu_pll_wait_for_lock(vdev, enable); in ivpu_pll_drive()
255 if (enable) { in ivpu_pll_drive()
272 static int ivpu_pll_enable(struct ivpu_device *vdev) in ivpu_pll_enable()
277 static int ivpu_pll_disable(struct ivpu_device *vdev) in ivpu_pll_disable()
282 static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev) in ivpu_boot_host_ss_rst_clr_assert()
293 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_rst_drive() argument
297 if (enable) { in ivpu_boot_host_ss_rst_drive()
310 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_clk_drive() argument
314 if (enable) { in ivpu_boot_host_ss_clk_drive()
327 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qreqn_check()
332 return -EIO; in ivpu_boot_noc_qreqn_check()
337 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qacceptn_check()
342 return -EIO; in ivpu_boot_noc_qacceptn_check()
347 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_noc_qdeny_check()
352 return -EIO; in ivpu_boot_noc_qdeny_check()
357 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qrenqn_check()
363 return -EIO; in ivpu_boot_top_noc_qrenqn_check()
368 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qacceptn_check()
374 return -EIO; in ivpu_boot_top_noc_qacceptn_check()
379 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_top_noc_qdeny_check()
385 return -EIO; in ivpu_boot_top_noc_qdeny_check()
390 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev) in ivpu_boot_host_ss_configure()
397 static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev) in ivpu_boot_vpu_idle_gen_disable()
402 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_axi_drive() argument
408 if (enable) in ivpu_boot_host_ss_axi_drive()
414 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); in ivpu_boot_host_ss_axi_drive()
427 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev) in ivpu_boot_host_ss_axi_enable()
432 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_host_ss_top_noc_drive() argument
438 if (enable) { in ivpu_boot_host_ss_top_noc_drive()
447 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); in ivpu_boot_host_ss_top_noc_drive()
460 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev) in ivpu_boot_host_ss_top_noc_enable()
465 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_trickle_drive() argument
469 if (enable) in ivpu_boot_pwr_island_trickle_drive()
477 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_drive() argument
481 if (enable) in ivpu_boot_pwr_island_drive()
489 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) in ivpu_boot_wait_for_pwr_island_status()
499 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_pwr_island_isolation_drive() argument
503 if (enable) in ivpu_boot_pwr_island_isolation_drive()
511 static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_dpu_active_drive() argument
515 if (enable) in ivpu_boot_dpu_active_drive()
523 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev) in ivpu_boot_pwr_domain_enable()
550 static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev) in ivpu_boot_pwr_domain_disable()
560 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev) in ivpu_boot_no_snoop_enable()
571 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev) in ivpu_boot_tbu_mmu_enable()
583 static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev) in ivpu_boot_soc_cpu_boot()
599 val = vdev->fw->entry_point >> 9; in ivpu_boot_soc_cpu_boot()
606 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); in ivpu_boot_soc_cpu_boot()
609 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable) in ivpu_boot_d0i3_drive() argument
621 if (enable) in ivpu_boot_d0i3_drive()
634 static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev) in ivpu_hw_37xx_info_init()
636 struct ivpu_hw_info *hw = vdev->hw; in ivpu_hw_37xx_info_init()
638 hw->tile_fuse = TILE_FUSE_ENABLE_BOTH; in ivpu_hw_37xx_info_init()
639 hw->sku = TILE_SKU_BOTH_MTL; in ivpu_hw_37xx_info_init()
640 hw->config = WP_CONFIG_2_TILE_4_3_RATIO; in ivpu_hw_37xx_info_init()
644 ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M); in ivpu_hw_37xx_info_init()
645 ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M); in ivpu_hw_37xx_info_init()
646 ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G); in ivpu_hw_37xx_info_init()
647 ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G); in ivpu_hw_37xx_info_init()
656 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) in ivpu_hw_37xx_reset()
662 ret = -EIO; in ivpu_hw_37xx_reset()
667 ret = -EIO; in ivpu_hw_37xx_reset()
673 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev) in ivpu_hw_37xx_d0i3_enable()
679 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); in ivpu_hw_37xx_d0i3_enable()
686 static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_d0i3_disable()
697 static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev) in ivpu_hw_37xx_power_up()
707 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret); in ivpu_hw_37xx_power_up()
726 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); in ivpu_hw_37xx_power_up()
732 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); in ivpu_hw_37xx_power_up()
738 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); in ivpu_hw_37xx_power_up()
743 static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev) in ivpu_hw_37xx_boot_fw()
752 static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev) in ivpu_hw_37xx_is_idle()
764 static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev) in ivpu_hw_37xx_power_down()
773 ret = -EIO; in ivpu_hw_37xx_power_down()
778 ret = -EIO; in ivpu_hw_37xx_power_down()
784 static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_wdt_disable()
788 /* Enable writing and set non-zero WDT value */ in ivpu_hw_37xx_wdt_disable()
792 /* Enable writing and disable watchdog timer */ in ivpu_hw_37xx_wdt_disable()
802 static u32 ivpu_hw_37xx_pll_to_freq(u32 ratio, u32 config) in ivpu_hw_37xx_pll_to_freq()
816 static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_pll_freq_get()
826 return ivpu_hw_37xx_pll_to_freq(pll_curr_ratio, vdev->hw->config); in ivpu_hw_37xx_reg_pll_freq_get()
829 static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_offset_get()
834 static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_size_get()
839 static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_telemetry_enable_get()
844 static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id) in ivpu_hw_37xx_reg_db_set()
846 u32 reg_stride = MTL_VPU_CPU_SS_DOORBELL_1 - MTL_VPU_CPU_SS_DOORBELL_0; in ivpu_hw_37xx_reg_db_set()
852 static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_ipc_rx_addr_get()
857 static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev) in ivpu_hw_37xx_reg_ipc_rx_count_get()
864 static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) in ivpu_hw_37xx_reg_ipc_tx_set()
869 static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_clear()
874 static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_enable()
882 static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_disable()
890 static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_wdt_nce_handler()
897 static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_wdt_mss_handler()
905 static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev) in ivpu_hw_37xx_irq_noc_firewall_handler()
913 static u32 ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq) in ivpu_hw_37xx_irqv_handler()
944 static u32 ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq) in ivpu_hw_37xx_irqb_handler()
989 static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr) in ivpu_hw_37xx_irq_handler()
999 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ in ivpu_hw_37xx_irq_handler()
1005 static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev) in ivpu_hw_37xx_diagnose_failure()