Lines Matching refs:rr_cfg
2779 struct rr_config *rr_cfg = (struct rr_config *) data; in gaudi2_write_lbw_range_register() local
2781 switch (rr_cfg->type) { in gaudi2_write_lbw_range_register()
2803 dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type); in gaudi2_write_lbw_range_register()
2807 reg_min_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_lbw_range_register()
2808 reg_max_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_lbw_range_register()
2810 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { in gaudi2_write_lbw_range_register()
2811 write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min)); in gaudi2_write_lbw_range_register()
2812 write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max)); in gaudi2_write_lbw_range_register()
2815 write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min)); in gaudi2_write_lbw_range_register()
2816 write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max)); in gaudi2_write_lbw_range_register()
2832 struct rr_config rr_cfg; in gaudi2_write_rr_to_all_lbw_rtrs() local
2850 rr_cfg.type = rr_type; in gaudi2_write_rr_to_all_lbw_rtrs()
2851 rr_cfg.index = rr_index; in gaudi2_write_rr_to_all_lbw_rtrs()
2852 rr_cfg.min = min_val; in gaudi2_write_rr_to_all_lbw_rtrs()
2853 rr_cfg.max = max_val; in gaudi2_write_rr_to_all_lbw_rtrs()
2856 block_ctx.data = &rr_cfg; in gaudi2_write_rr_to_all_lbw_rtrs()
2992 struct rr_config *rr_cfg = (struct rr_config *) data; in gaudi2_write_hbw_range_register() local
2995 switch (rr_cfg->type) { in gaudi2_write_hbw_range_register()
3025 dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type); in gaudi2_write_hbw_range_register()
3029 min_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_hbw_range_register()
3030 min_hi_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_hbw_range_register()
3031 max_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_hbw_range_register()
3032 max_hi_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_hbw_range_register()
3034 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { in gaudi2_write_hbw_range_register()
3035 val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) | in gaudi2_write_hbw_range_register()
3036 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min); in gaudi2_write_hbw_range_register()
3037 val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) | in gaudi2_write_hbw_range_register()
3038 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max); in gaudi2_write_hbw_range_register()
3040 val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) | in gaudi2_write_hbw_range_register()
3041 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min); in gaudi2_write_hbw_range_register()
3042 val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) | in gaudi2_write_hbw_range_register()
3043 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max); in gaudi2_write_hbw_range_register()
3060 struct rr_config rr_cfg; in gaudi2_write_hbw_rr_to_all_mstr_if() local
3078 rr_cfg.type = rr_type; in gaudi2_write_hbw_rr_to_all_mstr_if()
3079 rr_cfg.index = rr_index; in gaudi2_write_hbw_rr_to_all_mstr_if()
3080 rr_cfg.min = min_val; in gaudi2_write_hbw_rr_to_all_mstr_if()
3081 rr_cfg.max = max_val; in gaudi2_write_hbw_rr_to_all_mstr_if()
3084 block_ctx.data = &rr_cfg; in gaudi2_write_hbw_rr_to_all_mstr_if()
3134 struct rr_config *rr_cfg) in gaudi2_write_mmu_range_register() argument
3138 switch (rr_cfg->type) { in gaudi2_write_mmu_range_register()
3154 dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type); in gaudi2_write_mmu_range_register()
3158 min_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_mmu_range_register()
3159 min_hi_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_mmu_range_register()
3160 max_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_mmu_range_register()
3161 max_hi_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_mmu_range_register()
3164 WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min)); in gaudi2_write_mmu_range_register()
3165 WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min)); in gaudi2_write_mmu_range_register()
3166 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max)); in gaudi2_write_mmu_range_register()
3167 WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max)); in gaudi2_write_mmu_range_register()
3173 struct rr_config rr_cfg; in gaudi2_init_mmu_range_registers() local
3181 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE); in gaudi2_init_mmu_range_registers()
3182 rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address); in gaudi2_init_mmu_range_registers()
3183 rr_cfg.index = 0; in gaudi2_init_mmu_range_registers()
3184 rr_cfg.type = RR_TYPE_LONG; in gaudi2_init_mmu_range_registers()
3194 gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg); in gaudi2_init_mmu_range_registers()