2991 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;  in gaudi2_write_hbw_range_register()  local
2997 		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;  in gaudi2_write_hbw_range_register()
3004 		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;  in gaudi2_write_hbw_range_register()
3011 		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;  in gaudi2_write_hbw_range_register()
3018 		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;  in gaudi2_write_hbw_range_register()
3029 	min_lo_reg_offset += rr_cfg->index * sizeof(u32);  in gaudi2_write_hbw_range_register()
3050 	WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));  in gaudi2_write_hbw_range_register()
3136 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;  in gaudi2_write_mmu_range_register()  local
3140 		min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;  in gaudi2_write_mmu_range_register()
3147 		min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;  in gaudi2_write_mmu_range_register()
3158 	min_lo_reg_offset += rr_cfg->index * sizeof(u32);  in gaudi2_write_mmu_range_register()
3164 	WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));  in gaudi2_write_mmu_range_register()