3225 	u32 instance_offset;  in gaudi2_init_protection_bits()  local
3230 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;  in gaudi2_init_protection_bits()
3231 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_init_protection_bits()
3236 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;  in gaudi2_init_protection_bits()
3238 			NUM_OF_HIF_PER_DCORE, instance_offset,  in gaudi2_init_protection_bits()
3243 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;  in gaudi2_init_protection_bits()
3244 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_init_protection_bits()
3276 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;  in gaudi2_init_protection_bits()
3277 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_init_protection_bits()
3284 			instance_offset, gaudi2_pb_pdma0_arc,  in gaudi2_init_protection_bits()
3290 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;  in gaudi2_init_protection_bits()
3292 			instance_offset, gaudi2_pb_dcr0_edma0,  in gaudi2_init_protection_bits()
3300 			instance_offset, gaudi2_pb_dcr0_edma0_arc,  in gaudi2_init_protection_bits()
3307 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;  in gaudi2_init_protection_bits()
3312 				instance_offset, gaudi2_pb_dcr0_mme_sbte,  in gaudi2_init_protection_bits()
3361 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;  in gaudi2_init_protection_bits()
3362 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_init_protection_bits()
3447 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;  in gaudi2_init_protection_bits()
3448 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_init_protection_bits()
3454 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;  in gaudi2_init_protection_bits()
3457 			instance_offset, gaudi2_pb_arc_sched,  in gaudi2_init_protection_bits()
3463 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;  in gaudi2_init_protection_bits()
3465 			instance_offset, gaudi2_pb_xbar_mid,  in gaudi2_init_protection_bits()
3471 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;  in gaudi2_init_protection_bits()
3473 			instance_offset, gaudi2_pb_xbar_edge,  in gaudi2_init_protection_bits()
3512 	instance_offset = mmROT1_BASE - mmROT0_BASE;  in gaudi2_init_protection_bits()
3514 			instance_offset, gaudi2_pb_rot0,  in gaudi2_init_protection_bits()
3522 			HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_init_protection_bits()
3599 	u32 instance_offset;  in gaudi2_ack_protection_bits_errors()  local
3603 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;  in gaudi2_ack_protection_bits_errors()
3604 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_ack_protection_bits_errors()
3608 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;  in gaudi2_ack_protection_bits_errors()
3610 			NUM_OF_HIF_PER_DCORE, instance_offset,  in gaudi2_ack_protection_bits_errors()
3615 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;  in gaudi2_ack_protection_bits_errors()
3616 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_ack_protection_bits_errors()
3640 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;  in gaudi2_ack_protection_bits_errors()
3641 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_ack_protection_bits_errors()
3645 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_ack_protection_bits_errors()
3649 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;  in gaudi2_ack_protection_bits_errors()
3651 			instance_offset, gaudi2_pb_dcr0_edma0,  in gaudi2_ack_protection_bits_errors()
3657 			instance_offset, gaudi2_pb_dcr0_edma0_arc,  in gaudi2_ack_protection_bits_errors()
3662 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;  in gaudi2_ack_protection_bits_errors()
3667 				instance_offset, gaudi2_pb_dcr0_mme_sbte,  in gaudi2_ack_protection_bits_errors()
3706 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;  in gaudi2_ack_protection_bits_errors()
3707 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_ack_protection_bits_errors()
3758 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;  in gaudi2_ack_protection_bits_errors()
3759 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_ack_protection_bits_errors()
3764 	instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;  in gaudi2_ack_protection_bits_errors()
3766 			instance_offset, gaudi2_pb_hbm,  in gaudi2_ack_protection_bits_errors()
3770 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;  in gaudi2_ack_protection_bits_errors()
3772 			instance_offset, gaudi2_pb_arc_sched,  in gaudi2_ack_protection_bits_errors()
3776 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;  in gaudi2_ack_protection_bits_errors()
3778 			instance_offset, gaudi2_pb_xbar_mid,  in gaudi2_ack_protection_bits_errors()
3782 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;  in gaudi2_ack_protection_bits_errors()
3784 			instance_offset, gaudi2_pb_xbar_edge,  in gaudi2_ack_protection_bits_errors()
3807 	instance_offset = mmROT1_BASE - mmROT0_BASE;  in gaudi2_ack_protection_bits_errors()
3808 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_ack_protection_bits_errors()
3812 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_ack_protection_bits_errors()