4840 				u32 queue_id_base)  in gaudi2_init_qman_pq()  argument
4846 		q = &hdev->kernel_queues[queue_id_base + pq_id];  in gaudi2_init_qman_pq()
4882 				u32 queue_id_base)  in gaudi2_init_qman_pqc()  argument
4911 static u32 gaudi2_get_dyn_sp_reg(struct hl_device *hdev, u32 queue_id_base)  in gaudi2_get_dyn_sp_reg()  argument
4916 	switch (queue_id_base) {  in gaudi2_get_dyn_sp_reg()
4953 		dev_err(hdev->dev, "Unexpected h/w queue %d\n", queue_id_base);  in gaudi2_get_dyn_sp_reg()
4961 					u32 queue_id_base)  in gaudi2_init_qman_common()  argument
4968 	irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base);  in gaudi2_init_qman_common()
4972 	map_table_entry = gaudi2_qman_async_event_id[queue_id_base];  in gaudi2_init_qman_common()
4997 		u32 queue_id_base)  in gaudi2_init_qman()  argument
5002 		hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_CS_COMPLETION;  in gaudi2_init_qman()
5004 	gaudi2_init_qman_pq(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5006 	gaudi2_init_qman_pqc(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5007 	gaudi2_init_qman_common(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5286 	u32 queue_id_base, reg_base;  in gaudi2_init_dcore_mme()  local
5290 		queue_id_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0;  in gaudi2_init_dcore_mme()
5293 		queue_id_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0;  in gaudi2_init_dcore_mme()
5296 		queue_id_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0;  in gaudi2_init_dcore_mme()
5299 		queue_id_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0;  in gaudi2_init_dcore_mme()
5311 	reg_base = gaudi2_qm_blocks_bases[queue_id_base];  in gaudi2_init_dcore_mme()
5312 	gaudi2_init_qman(hdev, reg_base, queue_id_base);  in gaudi2_init_dcore_mme()
5349 	u32 queue_id_base;  in gaudi2_init_tpc_config()  local
5352 	queue_id_base = cfg_data->dcore_tpc_qid_base[dcore] + (inst * NUM_OF_PQ_PER_QMAN);  in gaudi2_init_tpc_config()
5361 	gaudi2_init_qman(hdev, mmDCORE0_TPC0_QM_BASE + offset, queue_id_base);  in gaudi2_init_tpc_config()