5762 static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, u32 stlb_base)  in gaudi2_mmu_init_common()  argument
5789 	WREG32(mmu_base + MMU_BYPASS_OFFSET, 0);  in gaudi2_mmu_init_common()
5802 	WREG32(mmu_base + MMU_ENABLE_OFFSET, 1);  in gaudi2_mmu_init_common()
5810 	u32 mmu_base, stlb_base;  in gaudi2_pci_mmu_init()  local
5816 	mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_pci_mmu_init()
5835 		RMWREG32_SHIFTED(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET,  in gaudi2_pci_mmu_init()
5846 	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_PMMU_SPI_SEI_ENABLE_MASK);  in gaudi2_pci_mmu_init()
5848 	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);  in gaudi2_pci_mmu_init()
5862 	u32 offset, mmu_base, stlb_base, hw_cap;  in gaudi2_dcore_hmmu_init()  local
5877 	mmu_base = mmDCORE0_HMMU0_MMU_BASE + offset;  in gaudi2_dcore_hmmu_init()
5880 	RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */,  in gaudi2_dcore_hmmu_init()
5898 	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_HMMU_SPI_SEI_ENABLE_MASK);  in gaudi2_dcore_hmmu_init()
5900 	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);  in gaudi2_dcore_hmmu_init()
8835 static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu,  in gaudi2_handle_page_error()  argument
8841 	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));  in gaudi2_handle_page_error()
8846 	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));  in gaudi2_handle_page_error()
8849 	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));  in gaudi2_handle_page_error()
8863 	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);  in gaudi2_handle_page_error()
8866 static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu)  in gaudi2_handle_access_error()  argument
8871 	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));  in gaudi2_handle_access_error()
8876 	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));  in gaudi2_handle_access_error()
8879 	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));  in gaudi2_handle_access_error()
8886 	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);  in gaudi2_handle_access_error()
8890 						u64 mmu_base, bool is_pmmu, u64 *event_mask)  in gaudi2_handle_mmu_spi_sei_generic()  argument
8895 	spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET);  in gaudi2_handle_mmu_spi_sei_generic()
8903 				gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, event_mask);  in gaudi2_handle_mmu_spi_sei_generic()
8905 				gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);  in gaudi2_handle_mmu_spi_sei_generic()
8915 	WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause);  in gaudi2_handle_mmu_spi_sei_generic()
8918 	WREG32(mmu_base + MMU_INTERRUPT_CLR_OFFSET, interrupt_clr);  in gaudi2_handle_mmu_spi_sei_generic()
9074 	u64 mmu_base;  in gaudi2_handle_mmu_spi_sei_err()  local
9079 		mmu_base = get_hmmu_base(event_type);  in gaudi2_handle_mmu_spi_sei_err()
9085 		mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_handle_mmu_spi_sei_err()
9091 	if (mmu_base == ULONG_MAX)  in gaudi2_handle_mmu_spi_sei_err()
9094 	error_count = gaudi2_handle_mmu_spi_sei_generic(hdev, event_type, mmu_base,  in gaudi2_handle_mmu_spi_sei_err()
10918 static int gaudi2_get_mmu_base(struct hl_device *hdev, u64 mmu_id, u32 *mmu_base)  in gaudi2_get_mmu_base()  argument
10922 		*mmu_base = mmDCORE0_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
10925 		*mmu_base = mmDCORE0_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
10928 		*mmu_base = mmDCORE0_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
10931 		*mmu_base = mmDCORE0_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
10934 		*mmu_base = mmDCORE1_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
10937 		*mmu_base = mmDCORE1_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
10940 		*mmu_base = mmDCORE1_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
10943 		*mmu_base = mmDCORE1_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
10946 		*mmu_base = mmDCORE2_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
10949 		*mmu_base = mmDCORE2_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
10952 		*mmu_base = mmDCORE2_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
10955 		*mmu_base = mmDCORE2_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
10958 		*mmu_base = mmDCORE3_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
10961 		*mmu_base = mmDCORE3_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
10964 		*mmu_base = mmDCORE3_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
10967 		*mmu_base = mmDCORE3_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
10970 		*mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_get_mmu_base()
10983 	u32 mmu_base;  in gaudi2_ack_mmu_error()  local
10988 	if (gaudi2_get_mmu_base(hdev, mmu_id, &mmu_base))  in gaudi2_ack_mmu_error()
10991 	gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, NULL);  in gaudi2_ack_mmu_error()
10992 	gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);  in gaudi2_ack_mmu_error()