7452 	u32 dcore_offset = dcore_id * DCORE_OFFSET;  in gaudi2_mmu_dcore_prepare()  local
7459 		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7460 		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7461 		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7462 		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7466 		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7467 		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7468 		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7469 		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7473 	WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid);  in gaudi2_mmu_dcore_prepare()
7481 		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val);  in gaudi2_mmu_dcore_prepare()
7482 		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7485 	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7486 	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7491 				dcore_offset + ports_offset, 0);  in gaudi2_mmu_dcore_prepare()
7493 				dcore_offset + ports_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7499 				dcore_offset + ports_offset, 0);  in gaudi2_mmu_dcore_prepare()
7501 				dcore_offset + ports_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
7504 	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
7505 	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()