4322 static void gaudi2_stop_dcore_dec(struct hl_device *hdev, int dcore_id)  in gaudi2_stop_dcore_dec()  argument
4335 		dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id;  in gaudi2_stop_dcore_dec()
4339 		offset = dcore_id * DCORE_OFFSET + dec_id * DCORE_VDEC_OFFSET;  in gaudi2_stop_dcore_dec()
4358 				dcore_id, dec_id);  in gaudi2_stop_dcore_dec()
4405 	int dcore_id;  in gaudi2_stop_dec()  local
4410 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_stop_dec()
4411 		gaudi2_stop_dcore_dec(hdev, dcore_id);  in gaudi2_stop_dec()
5283 static void gaudi2_init_dcore_mme(struct hl_device *hdev, int dcore_id,  in gaudi2_init_dcore_mme()  argument
5288 	switch (dcore_id) {  in gaudi2_init_dcore_mme()
5302 		dev_err(hdev->dev, "Invalid dcore id %u\n", dcore_id);  in gaudi2_init_dcore_mme()
5307 		reg_base = gaudi2_mme_acc_blocks_bases[dcore_id];  in gaudi2_init_dcore_mme()
5422 	u32 dcore_id, dec_id, dec_bit;  in gaudi2_init_dec()  local
5431 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_init_dec()
5433 			dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id;  in gaudi2_init_dec()
5440 					dcore_id * DCORE_OFFSET +  in gaudi2_init_dec()
5554 bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id)  in gaudi2_is_hmmu_enabled()  argument
5559 	hw_cap = HW_CAP_DCORE0_DMMU0 << (NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id);  in gaudi2_is_hmmu_enabled()
5568 static inline u32 get_hmmu_stlb_base(int dcore_id, int hmmu_id)  in get_hmmu_stlb_base()  argument
5572 	offset =  (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);  in get_hmmu_stlb_base()
5612 						int dcore_id, int hmmu_id,  in gaudi2_hmmu_invalidate_cache_trigger()  argument
5615 	u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);  in gaudi2_hmmu_invalidate_cache_trigger()
5621 						int dcore_id, int hmmu_id,  in gaudi2_hmmu_invalidate_cache_status_poll()  argument
5624 	u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);  in gaudi2_hmmu_invalidate_cache_status_poll()
5632 	int dcore_id, hmmu_id;  in gaudi2_hmmus_invalidate_cache()  local
5635 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_hmmus_invalidate_cache()
5637 			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))  in gaudi2_hmmus_invalidate_cache()
5640 			gaudi2_hmmu_invalidate_cache_trigger(hdev, dcore_id, hmmu_id, inv_params);  in gaudi2_hmmus_invalidate_cache()
5645 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_hmmus_invalidate_cache()
5649 			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))  in gaudi2_hmmus_invalidate_cache()
5652 			rc = gaudi2_hmmu_invalidate_cache_status_poll(hdev, dcore_id, hmmu_id,  in gaudi2_hmmus_invalidate_cache()
5857 static int gaudi2_dcore_hmmu_init(struct hl_device *hdev, int dcore_id,  in gaudi2_dcore_hmmu_init()  argument
5866 	dmmu_seq = NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id;  in gaudi2_dcore_hmmu_init()
5876 	offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);  in gaudi2_dcore_hmmu_init()
5911 	int rc, dcore_id, hmmu_id;  in gaudi2_hbm_mmu_init()  local
5913 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_hbm_mmu_init()
5915 			rc = gaudi2_dcore_hmmu_init(hdev, dcore_id, hmmu_id);  in gaudi2_hbm_mmu_init()
7425 static void gaudi2_mmu_vdec_dcore_prepare(struct hl_device *hdev, int dcore_id,  in gaudi2_mmu_vdec_dcore_prepare()  argument
7429 			dcore_vdec_id + DCORE_OFFSET * dcore_id;  in gaudi2_mmu_vdec_dcore_prepare()
7447 static void gaudi2_mmu_dcore_prepare(struct hl_device *hdev, int dcore_id, u32 asid)  in gaudi2_mmu_dcore_prepare()  argument
7452 	u32 dcore_offset = dcore_id * DCORE_OFFSET;  in gaudi2_mmu_dcore_prepare()
7457 	edma_seq_base = dcore_id * NUM_OF_EDMA_PER_DCORE;  in gaudi2_mmu_dcore_prepare()
7478 	if (dcore_id > 0) {  in gaudi2_mmu_dcore_prepare()
7511 		if (prop->decoder_enabled_mask & BIT(dcore_id * NUM_OF_DEC_PER_DCORE + vdec_id))  in gaudi2_mmu_dcore_prepare()
7512 			gaudi2_mmu_vdec_dcore_prepare(hdev, dcore_id, vdec_id, rw_asid, 0);  in gaudi2_mmu_dcore_prepare()
7944 	u32 hbw_rtr_id, lbw_rtr_id, dcore_id, dcore_rtr_id, eng_id, binned_idx;  in gaudi2_ack_module_razwi_event_handler()  local
8005 		dcore_id = module_idx / NUM_OF_EDMA_PER_DCORE;  in gaudi2_ack_module_razwi_event_handler()
8010 								dcore_id * SFT_DCORE_OFFSET;  in gaudi2_ack_module_razwi_event_handler()
8045 		dcore_id = hbw_rtr_id / NUM_OF_RTR_PER_DCORE;  in gaudi2_ack_module_razwi_event_handler()
8048 				dcore_id * DCORE_OFFSET +  in gaudi2_ack_module_razwi_event_handler()
10128 	int dcore_id;  in gaudi2_restore_user_sm_registers()  local
10156 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
10187 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
10206 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
10831 	u32 base = 0, dcore_id, dec_id;  in gaudi2_get_dec_base_addr()  local
10839 		dcore_id = core_id / NUM_OF_DEC_PER_DCORE;  in gaudi2_get_dec_base_addr()
10842 		base = mmDCORE0_DEC0_CMD_BASE + dcore_id * DCORE_OFFSET +  in gaudi2_get_dec_base_addr()