2304 	prop->cfg_base_address = CFG_BASE;  in gaudi2_set_fixed_properties()
2431 	prop->pcie_dbi_base_address = CFG_BASE + mmPCIE_DBI_BASE;  in gaudi2_set_fixed_properties()
2432 	prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;  in gaudi2_set_fixed_properties()
2478 	hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + (CFG_BASE - STM_FLASH_BASE_ADDR);  in gaudi2_pci_bars_map()
3074 		CFG_BASE + le32_to_cpu(dyn_regs->eng_arc_irq_ctrl);  in gaudi2_init_arcs()
3085 		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],  in gaudi2_scrub_arc_dccm()
3097 		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],  in gaudi2_scrub_arc_dccm()
3107 		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],  in gaudi2_scrub_arc_dccm()
3117 		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],  in gaudi2_scrub_arc_dccm()
3323 	region->region_base = CFG_BASE;  in gaudi2_set_pci_memory_regions()
3325 	region->offset_in_bar = CFG_BASE - STM_FLASH_BASE_ADDR;  in gaudi2_set_pci_memory_regions()
4863 	mtr_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);  in gaudi2_init_qman_cp()
4864 	mtr_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);  in gaudi2_init_qman_cp()
4865 	so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);  in gaudi2_init_qman_cp()
4866 	so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);  in gaudi2_init_qman_cp()
4887 	so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);  in gaudi2_init_qman_pqc()
4888 	so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);  in gaudi2_init_qman_pqc()
4969 	WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset));  in gaudi2_init_qman_common()
4970 	WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset));  in gaudi2_init_qman_common()
5027 			lower_32_bits(CFG_BASE + irq_handler_offset));  in gaudi2_init_dma_core()
5030 			upper_32_bits(CFG_BASE + irq_handler_offset));  in gaudi2_init_dma_core()
5153 	addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;  in gaudi2_arm_monitors_for_virt_msix_db()
5165 	addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + first_mon_offset;  in gaudi2_arm_monitors_for_virt_msix_db()
6788 	comp_addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 +  in gaudi2_send_job_to_kdma()
7869 	u64 razwi_addr = CFG_BASE;  in gaudi2_razwi_rr_lbw_shared_printf_info()
9979 	comp_addr = CFG_BASE + sob_addr;  in gaudi2_memset_device_memory()
10694 	fence_addr = CFG_BASE + gaudi2_qm_blocks_bases[prop->q_idx] +  in gaudi2_gen_wait_cb()
10859 		if (block_addr == CFG_BASE + gaudi2->mapped_blocks[i].address) {  in gaudi2_get_hw_block_id()
10891 	offset_in_bar = CFG_BASE + gaudi2->mapped_blocks[block_id].address - STM_FLASH_BASE_ADDR;  in gaudi2_block_mmap()