Lines Matching +full:0 +full:x000000

34 #define CA_WRITEBACK	(0x4)
49 	movi	a3, 0x25	/* For SMP/MX -- internal for writeback,
53 	movi	a3, 0x29	/* non-MX -- Most cores use Std Memory
71 	movi	a1, 0
78 #if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul
79 #define TEMP_MAPPING_VADDR 0x40000000
81 #define TEMP_MAPPING_VADDR 0x00000000
84 	/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
91 	/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
110 	 *	   Start at 0x60000000, wrap around, and end with 0x20000000
112 2:	movi	a4, 0x20000000
121 	movi	a6, 0x01000000
137 	movi	a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
138 	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK
142 	movi	a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
143 	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS
170 	movi	a0, 0
182 #if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU
183 #error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.
190 	.long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00
191 	.long 0x006600, 0x000000, 0x000000, 0x000000
192 	.long 0x000000, 0x000000, 0x000000, 0x000000
193 	.long 0x000000, 0x000000, 0x000000, 0x000000
200 	movi	a10, 0x20000000
210 	l32i	a9, a9, 0
220 	movi	a8, 0x20000000