Lines Matching +full:build +full:- +full:without +full:- +full:default +full:- +full:devices
1 # SPDX-License-Identifier: GPL-2.0
58 Xtensa processors are 32-bit RISC machines designed by Tensilica
63 a home page at <http://www.linux-xtensa.org/>.
82 default 100
99 default 0x6e400000
102 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
108 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
114 default XTENSA_VARIANT_FSF
117 bool "fsf - default (not generic) configuration"
121 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
128 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
152 default "dc232b" if XTENSA_VARIANT_DC232B
153 default "dc233c" if XTENSA_VARIANT_DC233C
154 default "fsf" if XTENSA_VARIANT_FSF
155 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
160 default y
163 Build a Conventional Kernel with full MMU support,
164 ie: it supports a TLB with auto-loading, page protection.
169 default n
179 default n
186 but only if these IRQs are not used. There will be a build warning
194 default y
207 Per default, unaligned memory accesses are disabled in user space.
221 byte and 2-byte access to memory attached to instruction bus.
228 This option is used to indicate that the system-on-a-chip (SOC)
236 and causes the IRQ numbers to be increased by 4 for devices
242 bool "Enable Symmetric multi-processing support"
251 int "Maximum number of CPUs (2-32)"
253 default "4"
260 controlled through /sys/devices/system/cpu.
266 default y
275 default n
288 default n
301 default KERNEL_ABI_DEFAULT
309 build.
311 If unsure, choose the default ABI.
314 bool "Default ABI"
316 Select this option to compile kernel code with the default ABI
319 cores without it use call0 ABI.
326 When this option is not selected the default toolchain ABI will
336 default USER_ABI_DEFAULT
340 If unsure, choose the default ABI.
343 bool "Default ABI only"
345 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
398 default XTENSA_PLATFORM_ISS
410 XT2000 is the name of Tensilica's feature-rich emulation platform.
428 default 3 if XTENSA_PLATFORM_XT2000
429 default 0
434 default 16
442 bool "Default bootloader kernel arguments"
447 default "console=ttyS0,38400 root=/dev/ram"
451 architectures, you should supply some command-line options at build
463 string "DTB to build into the kernel image"
468 default y
471 be disabled if the kernel is known to run without the bootloader.
477 default XTENSA_SIMCALL_ISS
498 tristate "Host file-based simulated block device support"
499 default n
502 Create block devices that map to files in the host file system.
507 int "Number of host file-based simulated block devices"
510 default 2
512 This is the default minimal number of created block devices.
520 default ""
528 default ""
530 Another simulated disk in a host file for a buildroot-independent
536 default n
547 default "0x0d0c0000"
555 bool "Use 8-bit access to XTFPGA LCD"
557 default n
559 LCD may be connected with 4- or 8-bit interface, 8-bit access may
560 only be used with 8-bit interface. Please consult prototyping user
568 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
576 This unfortunately won't work for U-Boot and likely also won't
582 xt-gdb can't place a Software Breakpoint in the 0XD region prior
590 Selecting this will cause U-Boot to set the KERNEL Load and Entry
596 bool "Kernel Execute-In-Place from ROM"
599 Execute-In-Place allows the kernel to run from non-volatile storage
602 to RAM. Read-write sections, such as the data section and stack,
619 default 0x22222222
623 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
624 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
643 2: WB, no-write-allocate cache,
650 default 0x00000000
658 If unsure, leave the default value here.
663 default 0xd0003000
672 default 0x60003000 if !MMU
673 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
674 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
680 If unsure, leave the default value here.
684 default XTENSA_VECTORS_IN_TEXT
688 configurations without VECBASE register where vectors are always
689 placed at their hardware-defined locations.
706 XIP-aware MTD support.
712 default 0x00000000
721 default 0x00000000
732 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
733 default 0x00000000
738 If unsure, leave the default value here.
743 default XTENSA_KSEG_MMU_V2
750 without cache.
758 with cache and to 0xc0000000 without cache.
766 with cache and to 0xc0000000 without cache.
777 default. However, the default MMUv2 setup only maps the
793 default "10"
799 overriding the default setting when ability to allocate very