platform/ce4100/falconfalls.dts

1 // SPDX-License-Identifier: GPL-2.0-only
3  * CE4100 on Falcon Falls
7 /dts-v1/;
11 	#address-cells = <1>;
12 	#size-cells = <1>;
15 		#address-cells = <1>;
16 		#size-cells = <0>;
20 			compatible = "intel,ce4100";
22 			lapic = <&lapic0>;
27 		#address-cells = <1>;
28 		#size-cells = <1>;
29 		compatible = "intel,ce4100-cp";
32 		ioapic1: interrupt-controller@fec00000 {
33 			#interrupt-cells = <2>;
34 			compatible = "intel,ce4100-ioapic";
35 			interrupt-controller;
40 			compatible = "intel,ce4100-hpet";
44 		lapic0: interrupt-controller@fee00000 {
45 			compatible = "intel,ce4100-lapic";
50 			#address-cells = <3>;
51 			#size-cells = <2>;
52 			compatible = "intel,ce4100-pci", "pci";
54 			bus-range = <0 0>;
59 			/* Secondary IO-APIC */
60 			ioapic2: interrupt-controller@0,1 {
61 				#interrupt-cells = <2>;
62 				compatible = "intel,ce4100-ioapic";
63 				interrupt-controller;
65 				assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
69 				#address-cells = <3>;
70 				#size-cells = <2>;
71 				compatible = "intel,ce4100-pci", "pci";
73 				bus-range = <1 1>;
77 				interrupt-parent = <&ioapic2>;
179 				entertainment-encryption@9,0 {
209 					#gpio-cells = <2>;
210 					#interrupt-cells = <2>;
218 					interrupt-controller;
219 					gpio-controller;
223 				i2c-controller@b,2 {
224 					#address-cells = <2>;
225 					#size-cells = <1>;
238 						#address-cells = <1>;
239 						#size-cells = <0>;
240 						compatible = "intel,ce4100-i2c-controller";
245 						#address-cells = <1>;
246 						#size-cells = <0>;
247 						compatible = "intel,ce4100-i2c-controller";
251 							#gpio-cells = <2>;
254 							gpio-controller;
259 						#address-cells = <1>;
260 						#size-cells = <0>;
261 						compatible = "intel,ce4100-i2c-controller";
265 							#gpio-cells = <2>;
268 							gpio-controller;
273 				smard-card@b,3 {
283 				spi-controller@b,4 {
284 					#address-cells = <1>;
285 					#size-cells = <0>;
298 						spi-max-frequency = <115200>;
304 						spi-max-frequency = <115200>;
310 						spi-max-frequency = <115200>;
383 				entertainment-encryption@10,0 {
392 				co-processor@11,0 {
413 				#address-cells = <2>;
414 				#size-cells = <1>;
420 					compatible = "intel,ce4100-rtc", "motorola,mc146818";
422 					interrupt-parent = <&ioapic1>;
423 					ctrl-reg = <2>;
424 					freq-reg = <0x26>;