Lines Matching refs:IA32_EDX
100 #define IA32_EDX (0x2) macro
324 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_le_r64()
329 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_to_le_r64()
372 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_be_r64()
377 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_to_be_r64()
458 EMIT2(0x31, add_2reg(0xC0, IA32_EDX, IA32_EDX)); in emit_ia32_div_mod_r()
464 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_div_mod_r()
467 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EDX)); in emit_ia32_div_mod_r()
530 u8 dreg = dstk ? IA32_EDX : dst; in emit_ia32_alu_r()
538 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst)); in emit_ia32_alu_r()
604 u8 sreg = IA32_EDX; in emit_ia32_alu_i()
612 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val); in emit_ia32_alu_i()
703 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_neg64()
708 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_neg64()
737 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_r64()
742 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_lsh_r64()
790 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_r64()
795 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_arsh_r64()
843 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_r64()
848 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_rsh_r64()
896 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_i64()
901 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_lsh_i64()
944 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_i64()
949 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_rsh_i64()
993 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_i64()
998 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_ia32_arsh_i64()
1093 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX)); in emit_ia32_mul_r64()
1153 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX)); in emit_ia32_mul_i64()
1254 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1])); in emit_epilogue()
1317 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0])); in emit_bpf_tail_call()
1320 EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX), in emit_bpf_tail_call()
1362 EMIT2(0x85, add_2reg(0xC0, IA32_EDX, IA32_EDX)); in emit_bpf_tail_call()
1368 EMIT3(0x8B, add_2reg(0x40, IA32_EDX, IA32_EDX), in emit_bpf_tail_call()
1371 EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE); in emit_bpf_tail_call()
1572 const u8 arg_regs[] = { IA32_EAX, IA32_EDX, IA32_ECX }; in emit_kfunc_call()
1647 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX), in emit_kfunc_call()
1966 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in do_jit()
1970 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EDX)); in do_jit()
1983 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX), in do_jit()
1986 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX), in do_jit()
1993 IA32_EDX), in do_jit()
1998 IA32_EDX)); in do_jit()
2002 IA32_EDX), in do_jit()
2006 IA32_EDX)); in do_jit()
2036 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX), in do_jit()
2039 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX), in do_jit()
2044 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX), in do_jit()
2048 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EDX)); in do_jit()
2067 add_2reg(0x80, IA32_EAX, IA32_EDX), in do_jit()
2072 IA32_EDX), in do_jit()
2076 add_2reg(0xC0, dst_hi, IA32_EDX)); in do_jit()
2119 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), in do_jit()
2133 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX), in do_jit()
2163 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2173 IA32_EDX), in do_jit()
2201 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2210 IA32_EDX), in do_jit()
2234 u8 dreg_hi = IA32_EDX; in do_jit()
2244 IA32_EDX), in do_jit()
2278 u8 dreg_hi = IA32_EDX; in do_jit()
2289 IA32_EDX), in do_jit()
2334 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2345 IA32_EDX), in do_jit()
2381 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2391 IA32_EDX), in do_jit()