28 static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)  in amd_pmc_idx_to_pmc()  argument
30 	unsigned int num_counters = pmu->nr_arch_gp_counters;  in amd_pmc_idx_to_pmc()
35 	return &pmu->gp_counters[array_index_nospec(pmc_idx, num_counters)];  in amd_pmc_idx_to_pmc()
38 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,  in get_gp_pmc_amd()  argument
41 	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);  in get_gp_pmc_amd()
73 	return amd_pmc_idx_to_pmc(pmu, idx);  in get_gp_pmc_amd()
83 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_is_valid_rdpmc_ecx()  local
87 	return idx < pmu->nr_arch_gp_counters;  in amd_is_valid_rdpmc_ecx()
99 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_msr_idx_to_pmc()  local
102 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_msr_idx_to_pmc()
103 	pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_msr_idx_to_pmc()
110 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_is_valid_msr()  local
114 		return pmu->version > 0;  in amd_is_valid_msr()
120 		return pmu->version > 1;  in amd_is_valid_msr()
123 		    msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters)  in amd_is_valid_msr()
124 			return pmu->version > 1;  in amd_is_valid_msr()
133 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_get_msr()  local
138 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_get_msr()
144 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_get_msr()
155 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_set_msr()  local
161 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_set_msr()
168 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_set_msr()
170 		data &= ~pmu->reserved_bits;  in amd_pmu_set_msr()
183 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_refresh()  local
186 	pmu->version = 1;  in amd_pmu_refresh()
188 		pmu->version = 2;  in amd_pmu_refresh()
196 		pmu->nr_arch_gp_counters = ebx.split.num_core_pmc;  in amd_pmu_refresh()
198 		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;  in amd_pmu_refresh()
200 		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;  in amd_pmu_refresh()
203 	pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters,  in amd_pmu_refresh()
206 	if (pmu->version > 1) {  in amd_pmu_refresh()
207 		pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1);  in amd_pmu_refresh()
208 		pmu->global_status_mask = pmu->global_ctrl_mask;  in amd_pmu_refresh()
211 	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;  in amd_pmu_refresh()
212 	pmu->reserved_bits = 0xfffffff000280000ull;  in amd_pmu_refresh()
213 	pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;  in amd_pmu_refresh()
215 	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;  in amd_pmu_refresh()
216 	pmu->nr_arch_fixed_counters = 0;  in amd_pmu_refresh()
217 	bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters);  in amd_pmu_refresh()
222 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_init()  local
229 		pmu->gp_counters[i].type = KVM_PMC_GP;  in amd_pmu_init()
230 		pmu->gp_counters[i].vcpu = vcpu;  in amd_pmu_init()
231 		pmu->gp_counters[i].idx = i;  in amd_pmu_init()
232 		pmu->gp_counters[i].current_config = 0;  in amd_pmu_init()