1 /*  Generic MTRR (Memory Type Range Register) driver.
3     Copyright (C) 1997-2000  Richard Gooch
29     on 6-7 March 2002.
31     System Programming Guide; Section 9.11. (1997 edition - PPro).
68 /*  Returns non-zero if we have the write-combining memory type  */
77 		 * write-combining. Don't allow it and leave room for other  in have_wrcomb()
80 		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&  in have_wrcomb()
81 		    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&  in have_wrcomb()
82 		    dev->revision <= 5) {  in have_wrcomb()
83 			pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");  in have_wrcomb()
89 		 * write combining memory may resulting in data corruption  in have_wrcomb()
91 		if (dev->vendor == PCI_VENDOR_ID_INTEL &&  in have_wrcomb()
92 		    dev->device == PCI_DEVICE_ID_INTEL_82451NX) {  in have_wrcomb()
93 			pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");  in have_wrcomb()
99 	return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;  in have_wrcomb()
119  * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
129 	mtrr_if->set(data->smp_reg, data->smp_base,  in mtrr_rendezvous_handler()
130 		     data->smp_size, data->smp_type);  in mtrr_rendezvous_handler()
143  * set_mtrr - update mtrrs on all processors
154  * 4. Enter no-fill cache mode
170  * (the CPU vendors may each do it differently, so we call mtrr_if->set()
191  * mtrr_add_page - Add a memory type region
197  * Memory type region registers control the caching on newer Intel and
214  * %MTRR_TYPE_UNCACHABLE - No caching
216  * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
218  * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
220  * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
233 		return -ENXIO;  in mtrr_add_page()
235 	error = mtrr_if->validate_add_page(base, size, type);  in mtrr_add_page()
241 		return -EINVAL;  in mtrr_add_page()
244 	/* If the type is WC, check that this processor supports it */  in mtrr_add_page()
246 		pr_warn("your processor doesn't support write-combining\n");  in mtrr_add_page()
247 		return -ENOSYS;  in mtrr_add_page()
252 		return -EINVAL;  in mtrr_add_page()
255 	if ((base | (base + size - 1)) >>  in mtrr_add_page()
256 	    (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {  in mtrr_add_page()
258 		return -EINVAL;  in mtrr_add_page()
261 	error = -EINVAL;  in mtrr_add_page()
262 	replace = -1;  in mtrr_add_page()
264 	/* No CPU hotplug when we change MTRR entries */  in mtrr_add_page()
270 		mtrr_if->get(i, &lbase, &lsize, &ltype);  in mtrr_add_page()
271 		if (!lsize || base > lbase + lsize - 1 ||  in mtrr_add_page()
272 		    base + size - 1 < lbase)  in mtrr_add_page()
278 		if (base < lbase || base + size - 1 > lbase + lsize - 1) {  in mtrr_add_page()
280 			    base + size - 1 >= lbase + lsize - 1) {  in mtrr_add_page()
283 					replace = replace == -1 ? i : -2;  in mtrr_add_page()
307 	i = mtrr_if->get_free_region(base, size, replace);  in mtrr_add_page()
322 		pr_info("no more MTRRs available\n");  in mtrr_add_page()
333 	if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {  in mtrr_check()
337 		return -1;  in mtrr_check()
343  * mtrr_add - Add a memory type region
349  * Memory type region registers control the caching on newer Intel and
366  * %MTRR_TYPE_UNCACHABLE - No caching
368  * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
370  * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
372  * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
381 		return -ENODEV;  in mtrr_add()
383 		return -EINVAL;  in mtrr_add()
389  * mtrr_del_page - delete a memory type region
407 	int error = -EINVAL;  in mtrr_del_page()
410 		return -ENODEV;  in mtrr_del_page()
413 	/* No CPU hotplug when we change MTRR entries */  in mtrr_del_page()
419 			mtrr_if->get(i, &lbase, &lsize, &ltype);  in mtrr_del_page()
426 			Dprintk("no MTRR for %lx000,%lx000 found\n", base, size);  in mtrr_del_page()
434 	mtrr_if->get(reg, &lbase, &lsize, &ltype);  in mtrr_del_page()
443 	if (--mtrr_usage_table[reg] < 1)  in mtrr_del_page()
453  * mtrr_del - delete a memory type region
469 		return -ENODEV;  in mtrr_del()
471 		return -EINVAL;  in mtrr_del()
476  * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
481  * attempts to add a WC MTRR covering size bytes starting at base and
499 		pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",  in arch_phys_wc_add()
500 			(void *)base, (void *)(base + size - 1));  in arch_phys_wc_add()
508  * arch_phys_wc_del - undoes arch_phys_wc_add
520 		mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);  in arch_phys_wc_del()
526  * arch_phys_wc_index - translates arch_phys_wc_add's return value
532  * Note: There is no legitimate use for this function, except possibly
539 		return -1;  in arch_phys_wc_index()
541 		return handle - MTRR_TO_PHYS_WC_OFFSET;  in arch_phys_wc_index()
548  * mtrr_bp_init - initialize MTRRs on the boot CPU
559 	phys_hi_rsvd = GENMASK(31, boot_cpu_data.x86_phys_bits - 32);  in mtrr_bp_init()
568 		pr_info("MTRRs set to read-only\n");  in mtrr_bp_init()
583 			config = mtrr_if->var_regs;  in mtrr_bp_init()
605  * mtrr_save_state - Save current fixed-range MTRR state of the first