Lines Matching +full:deep +full:- +full:touch
1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) {
107 if (c->x86 != 6)
109 switch (c->x86_vfm) {
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
177 if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&
178 c->x86_stepping == spectre_bad_microcodes[i].stepping)
179 return (c->microcode <= spectre_bad_microcodes[i].microcode);
248 nr_keyids = (1UL << keyid_bits) - 1;
265 c->x86_phys_bits -= keyid_bits;
273 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
276 c->cpuid_level = cpuid_eax(0);
281 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
282 (c->x86 == 0x6 && c->x86_model >= 0x0e))
285 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
286 c->microcode = intel_get_microcode_revision();
312 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&
313 c->microcode < 0x20e) {
322 if (c->x86 == 15 && c->x86_cache_alignment == 64)
323 c->x86_cache_alignment = 128;
327 if (c->x86 == 0xF && c->x86_model == 0x3
328 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
329 c->x86_phys_bits = 36;
332 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
333 * with P/T states and does not stop in deep C-states.
336 * cabinets - we turn it off in that case explicitly.)
338 if (c->x86_power & (1 << 8)) {
344 switch (c->x86_vfm) {
363 if (c->x86 == 6 && c->x86_model < 15)
370 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
389 if (c->x86_vfm == INTEL_QUARK_X1000) {
394 if (c->cpuid_level >= 0x00000001) {
404 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
452 if (!c->cpu_index)
458 if (c->x86 == 5 &&
459 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
460 c->x86_model <= 3) {
487 if (c->x86 == 5 && c->x86_model < 9) {
492 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
502 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
520 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
534 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
535 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
543 switch (c->x86) {
548 case 6: /* PII/PIII only like movsl with 8-byte alignment */
551 case 15: /* P4 is OK down to 8-byte alignment */
639 if (c->cpuid_level > 9) {
660 (c->x86_vfm == INTEL_CORE2_DUNNINGTON ||
661 c->x86_vfm == INTEL_NEHALEM_EX ||
662 c->x86_vfm == INTEL_WESTMERE_EX))
666 (c->x86_vfm == INTEL_ATOM_GOLDMONT ||
667 c->x86_vfm == INTEL_LUNARLAKE_M))
671 if (c->x86 == 15)
672 c->x86_cache_alignment = c->x86_clflush_size * 2;
673 if (c->x86 == 6)
681 if (c->x86 == 6) {
682 unsigned int l2 = c->x86_cache_size;
685 switch (c->x86_model) {
696 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
697 p = "Celeron-A";
707 strcpy(c->x86_model_id, p);
710 if (c->x86 == 15)
712 if (c->x86 == 6)
738 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
742 * Intel Quark SoC X1000 contains a 4-way set associative
745 if ((c->x86 == 5) && (c->x86_model == 9))
773 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
775 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
776 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
777 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
778 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
780 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
781 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
782 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
783 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
784 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
785 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
787 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
792 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
793 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
794 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
796 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
797 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
798 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
799 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
800 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
801 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
802 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
803 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
804 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
805 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
806 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
807 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
808 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
905 if (c->cpuid_level < 2)
932 [0] = "486 DX-25/33",
933 [1] = "486 DX-50",
938 [7] = "486 DX/2-WB",
940 [9] = "486 DX/4-WB"
945 [0] = "Pentium 60/66 A-step",
947 [2] = "Pentium 75 - 200",
950 [7] = "Mobile Pentium 75 - 200",
957 [0] = "Pentium Pro A-step",
1156 * If a CPU goes offline with pending delayed work to re-enable split lock
1159 * different CPU probably won't re-enable split lock detection. This is a
1163 * Unconditionally re-enable detection here.
1177 if (!current->reported_split_lock)
1179 current->comm, current->pid, ip);
1180 current->reported_split_lock = 1;
1193 if (down_interruptible(&buslock_sem) == -EINTR)
1216 current->comm, current->pid,
1219 current->thread.error_code = 0;
1220 current->thread.trap_nr = X86_TRAP_AC;
1252 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1254 split_lock_warn(regs->ip);
1271 current->comm, current->pid, regs->ip);
1280 * CPU models that are known to have the per-core split-lock detection
1335 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1340 pr_info("#DB: warning on user-space bus_locks\n");
1345 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1347 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1349 " from non-WB" : "");
1369 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU