54 u64 x86_spec_ctrl_base;  variable
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
139 		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);  in cpu_select_mitigations()
146 		x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;  in cpu_select_mitigations()
1573 	x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;  in spec_ctrl_disable_kernel_rrsba()
1574 	update_spec_ctrl(x86_spec_ctrl_base);  in spec_ctrl_disable_kernel_rrsba()
1634 	x86_spec_ctrl_base |= SPEC_CTRL_BHI_DIS_S;  in spec_ctrl_bhi_dis()
1635 	update_spec_ctrl(x86_spec_ctrl_base);  in spec_ctrl_bhi_dis()
1767 			x86_spec_ctrl_base |= SPEC_CTRL_IBRS;  in spectre_v2_select_mitigation()
1768 			update_spec_ctrl(x86_spec_ctrl_base);  in spectre_v2_select_mitigation()
1885 	u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);  in update_stibp_msr()
1892 	u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;  in update_stibp_strict()
1897 	if (mask == x86_spec_ctrl_base)  in update_stibp_strict()
1902 	x86_spec_ctrl_base = mask;  in update_stibp_strict()
2116 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;  in __ssb_select_mitigation()
2117 			update_spec_ctrl(x86_spec_ctrl_base);  in __ssb_select_mitigation()
2370 		update_spec_ctrl(x86_spec_ctrl_base);  in x86_spec_ctrl_setup_ap()