include/asm/perf_event.h

17 #define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1			      0xc2
20 #define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1			     0x187
23 #define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
33 #define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL
35 #define INTEL_FIXED_BITS_MASK				0xFULL
37 #define INTEL_FIXED_0_KERNEL				(1ULL << 0)
56 	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
59 	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
65 	(0xFULL << AMD64_L3_SLICE_SHIFT)
67 	(0x7ULL << AMD64_L3_SLICE_SHIFT)
71 	(0xFFULL << AMD64_L3_THREAD_SHIFT)
73 	(0x3ULL << AMD64_L3_THREAD_SHIFT)
80 	(0x7ULL << AMD64_L3_COREID_SHIFT)
119 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
120 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
121 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
128 #define PEBS_DATACFG_MEMINFO	BIT_ULL(0)
179 #define ARCH_PERFMON_EXT_LEAF			0x00000023
180 #define ARCH_PERFMON_NUM_COUNTER_LEAF		0x1
285 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d
296  * The pseudo event-code for a fixed-mode PMC must be 0x00.
297  * The pseudo umask-code is 0xX. The X equals the index of the fixed
298  * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
304 #define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
305 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)
308 #define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
311 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
312 #define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
316 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
317 #define MSR_ARCH_PERFMON_FIXED_CTR3	0x30c
323 	return !(code & 0xff);  in use_fixed_pseudo_encoding()
342 #define INTEL_PMC_IDX_TD_RETIRING		(INTEL_PMC_IDX_METRIC_BASE + 0)
351 #define INTEL_PMC_MSK_TOPDOWN			((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
359  * For the metric events, the pseudo event-code is 0x00.
361  * space, 0x80.
363 #define INTEL_TD_SLOTS				0x0400	/* TOPDOWN.SLOTS */
365 #define INTEL_TD_METRIC_RETIRING		0x8000	/* Retiring metric */
366 #define INTEL_TD_METRIC_BAD_SPEC		0x8100	/* Bad speculation metric */
367 #define INTEL_TD_METRIC_FE_BOUND		0x8200	/* FE bound metric */
368 #define INTEL_TD_METRIC_BE_BOUND		0x8300	/* BE bound metric */
370 #define INTEL_TD_METRIC_HEAVY_OPS		0x8400  /* Heavy Operations metric */
371 #define INTEL_TD_METRIC_BR_MISPREDICT		0x8500  /* Branch Mispredict metric */
372 #define INTEL_TD_METRIC_FETCH_LAT		0x8600  /* Fetch Latency metric */
373 #define INTEL_TD_METRIC_MEM_BOUND		0x8700  /* Memory bound metric */
389 			(~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
418  * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
421 #define INTEL_FIXED_VLBR_EVENT	0x1b00
453 #define EXT_PERFMON_DEBUG_FEATURES		0x80000022
459 #define IBS_CPUID_FEATURES		0x8000001b
463  * bit 0 is used to indicate the existence of IBS.
465 #define IBS_CAPS_AVAIL			(1U<<0)
485 #define IBSCTL				0x1cc
487 #define IBSCTL_LVT_OFFSET_MASK		0x0F
494 #define IBS_FETCH_CNT		0xFFFF0000ULL
495 #define IBS_FETCH_MAX_CNT	0x0000FFFFULL
502 #define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)
503 #define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)
508 #define IBS_OP_MAX_CNT		0x0000FFFFULL
509 #define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
510 #define IBS_OP_MAX_CNT_EXT_MASK	(0x7FULL<<20)	/* separate upper 7 bits */
517 static inline u32 get_ibs_caps(void) { return 0; }  in get_ibs_caps()
526  * unused and ABI specified to be 0, so nobody should care what we do with
554 	(regs)->sp = (unsigned long)__builtin_frame_address(0);	\
556 	regs->flags = 0;					\
579 	memset(cap, 0, sizeof(*cap));  in perf_get_x86_pmu_capability()
584 	return 0;  in perf_get_hw_event_config()
598 	memset(lbr, 0, sizeof(*lbr));  in x86_perf_get_lbr()