Lines Matching +full:0 +full:xfec00000
14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_ID 0x20
25 #define APIC_LVR 0x30
26 #define APIC_LVR_MASK 0xFF00FF
28 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
29 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
31 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
35 #define APIC_XAPIC(x) ((x) >= 0x14)
36 #define APIC_EXT_SPACE(x) ((x) & 0x80000000)
37 #define APIC_TASKPRI 0x80
38 #define APIC_TPRI_MASK 0xFFu
39 #define APIC_ARBPRI 0x90
40 #define APIC_ARBPRI_MASK 0xFFu
41 #define APIC_PROCPRI 0xA0
42 #define APIC_EOI 0xB0
43 #define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */
44 #define APIC_RRR 0xC0
45 #define APIC_LDR 0xD0
46 #define APIC_LDR_MASK (0xFFu << 24)
47 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
49 #define APIC_ALL_CPUS 0xFFu
50 #define APIC_DFR 0xE0
51 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
52 #define APIC_DFR_FLAT 0xFFFFFFFFul
53 #define APIC_SPIV 0xF0
57 #define APIC_ISR 0x100
58 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
59 #define APIC_TMR 0x180
60 #define APIC_IRR 0x200
61 #define APIC_ESR 0x280
62 #define APIC_ESR_SEND_CS 0x00001
63 #define APIC_ESR_RECV_CS 0x00002
64 #define APIC_ESR_SEND_ACC 0x00004
65 #define APIC_ESR_RECV_ACC 0x00008
66 #define APIC_ESR_SENDILL 0x00020
67 #define APIC_ESR_RECVILL 0x00040
68 #define APIC_ESR_ILLREGA 0x00080
69 #define APIC_LVTCMCI 0x2f0
70 #define APIC_ICR 0x300
71 #define APIC_DEST_SELF 0x40000
72 #define APIC_DEST_ALLINC 0x80000
73 #define APIC_DEST_ALLBUT 0xC0000
74 #define APIC_ICR_RR_MASK 0x30000
75 #define APIC_ICR_RR_INVALID 0x00000
76 #define APIC_ICR_RR_INPROG 0x10000
77 #define APIC_ICR_RR_VALID 0x20000
78 #define APIC_INT_LEVELTRIG 0x08000
79 #define APIC_INT_ASSERT 0x04000
80 #define APIC_ICR_BUSY 0x01000
81 #define APIC_DEST_LOGICAL 0x00800
82 #define APIC_DEST_PHYSICAL 0x00000
83 #define APIC_DM_FIXED 0x00000
84 #define APIC_DM_FIXED_MASK 0x00700
85 #define APIC_DM_LOWEST 0x00100
86 #define APIC_DM_SMI 0x00200
87 #define APIC_DM_REMRD 0x00300
88 #define APIC_DM_NMI 0x00400
89 #define APIC_DM_INIT 0x00500
90 #define APIC_DM_STARTUP 0x00600
91 #define APIC_DM_EXTINT 0x00700
92 #define APIC_VECTOR_MASK 0x000FF
93 #define APIC_ICR2 0x310
94 #define GET_XAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
96 #define APIC_LVTT 0x320
97 #define APIC_LVTTHMR 0x330
98 #define APIC_LVTPC 0x340
99 #define APIC_LVT0 0x350
100 #define APIC_LVT_TIMER_ONESHOT (0 << 17)
108 #define APIC_MODE_MASK 0x700
109 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
110 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
111 #define APIC_MODE_FIXED 0x0
112 #define APIC_MODE_NMI 0x4
113 #define APIC_MODE_EXTINT 0x7
114 #define APIC_LVT1 0x360
115 #define APIC_LVTERR 0x370
116 #define APIC_TMICT 0x380
117 #define APIC_TMCCT 0x390
118 #define APIC_TDCR 0x3E0
119 #define APIC_SELF_IPI 0x3F0
121 #define APIC_TDR_DIV_1 0xB
122 #define APIC_TDR_DIV_2 0x0
123 #define APIC_TDR_DIV_4 0x1
124 #define APIC_TDR_DIV_8 0x2
125 #define APIC_TDR_DIV_16 0x3
126 #define APIC_TDR_DIV_32 0x8
127 #define APIC_TDR_DIV_64 0x9
128 #define APIC_TDR_DIV_128 0xA
129 #define APIC_EFEAT 0x400
130 #define APIC_ECTRL 0x410
131 #define APIC_EILVTn(n) (0x500 + 0x10 * n)
135 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
136 #define APIC_EILVT_MSG_FIX 0x0
137 #define APIC_EILVT_MSG_SMI 0x2
138 #define APIC_EILVT_MSG_NMI 0x4
139 #define APIC_EILVT_MSG_EXT 0x7
143 #define APIC_BASE_MSR 0x800
144 #define APIC_X2APIC_ID_MSR 0x802
220 /*0A0*/ const
227 /*0B0*/ struct { /* End Of Interrupt Register */
232 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
234 /*0D0*/ struct { /* Logical Destination Register */
240 /*0E0*/ struct { /* Destination Format Register */
246 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
428 #define BAD_APICID 0xFFu
430 #define BAD_APICID 0xFFFFu
434 APIC_DELIVERY_MODE_FIXED = 0,