200 static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)  in nhmex_uncore_msr_init_box()  argument
205 static void nhmex_uncore_msr_exit_box(struct intel_uncore_box *box)  in nhmex_uncore_msr_exit_box()  argument
210 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)  in nhmex_uncore_msr_disable_box()  argument
212 	unsigned msr = uncore_msr_box_ctl(box);  in nhmex_uncore_msr_disable_box()
217 		config &= ~((1ULL << uncore_num_counters(box)) - 1);  in nhmex_uncore_msr_disable_box()
219 		if (uncore_msr_fixed_ctl(box))  in nhmex_uncore_msr_disable_box()
225 static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)  in nhmex_uncore_msr_enable_box()  argument
227 	unsigned msr = uncore_msr_box_ctl(box);  in nhmex_uncore_msr_enable_box()
232 		config |= (1ULL << uncore_num_counters(box)) - 1;  in nhmex_uncore_msr_enable_box()
234 		if (uncore_msr_fixed_ctl(box))  in nhmex_uncore_msr_enable_box()
240 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_uncore_msr_disable_event()  argument
245 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_uncore_msr_enable_event()  argument
251 	else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)  in nhmex_uncore_msr_enable_event()
350 static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_bbox_hw_config()  argument
367 	if (box->pmu->pmu_idx == 0)  in nhmex_bbox_hw_config()
377 static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_bbox_msr_enable_event()  argument
441 static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_sbox_hw_config()  argument
452 	if (box->pmu->pmu_idx == 0)  in nhmex_sbox_hw_config()
462 static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_sbox_msr_enable_event()  argument
553 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)  in nhmex_mbox_get_shared_reg()  argument
561 		er = &box->shared_regs[idx];  in nhmex_mbox_get_shared_reg()
586 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];  in nhmex_mbox_get_shared_reg()
614 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)  in nhmex_mbox_put_shared_reg()  argument
619 		er = &box->shared_regs[idx];  in nhmex_mbox_put_shared_reg()
625 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];  in nhmex_mbox_put_shared_reg()
669 nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_mbox_get_constraint()  argument
680 		if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))  in nhmex_mbox_get_constraint()
686 		if (!nhmex_mbox_get_shared_reg(box, idx[i],  in nhmex_mbox_get_constraint()
694 	    (uncore_box_is_fake(box) || !reg2->alloc) &&  in nhmex_mbox_get_constraint()
695 	    !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))  in nhmex_mbox_get_constraint()
704 	if (!uncore_box_is_fake(box)) {  in nhmex_mbox_get_constraint()
732 		nhmex_mbox_put_shared_reg(box, idx[0]);  in nhmex_mbox_get_constraint()
734 		nhmex_mbox_put_shared_reg(box, idx[1]);  in nhmex_mbox_get_constraint()
738 static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_mbox_put_constraint()  argument
743 	if (uncore_box_is_fake(box))  in nhmex_mbox_put_constraint()
747 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));  in nhmex_mbox_put_constraint()
749 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));  in nhmex_mbox_put_constraint()
753 		nhmex_mbox_put_shared_reg(box, reg2->idx);  in nhmex_mbox_put_constraint()
765 static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_mbox_hw_config()  argument
767 	struct intel_uncore_type *type = box->pmu->type;  in nhmex_mbox_hw_config()
784 		msr = er->msr + type->msr_offset * box->pmu->pmu_idx;  in nhmex_mbox_hw_config()
811 		if (box->pmu->pmu_idx == 0)  in nhmex_mbox_hw_config()
819 static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)  in nhmex_mbox_shared_reg_config()  argument
826 		return box->shared_regs[idx].config;  in nhmex_mbox_shared_reg_config()
828 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];  in nhmex_mbox_shared_reg_config()
835 static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_mbox_msr_enable_event()  argument
845 			nhmex_mbox_shared_reg_config(box, idx));  in nhmex_mbox_msr_enable_event()
849 			nhmex_mbox_shared_reg_config(box, idx));  in nhmex_mbox_msr_enable_event()
944 static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_rbox_alter_er()  argument
978 nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_rbox_get_constraint()  argument
989 	if (!uncore_box_is_fake(box) && reg1->alloc)  in nhmex_rbox_get_constraint()
1001 	er = &box->shared_regs[er_idx];  in nhmex_rbox_get_constraint()
1052 		if (!uncore_box_is_fake(box)) {  in nhmex_rbox_get_constraint()
1054 				nhmex_rbox_alter_er(box, event);  in nhmex_rbox_get_constraint()
1062 static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_rbox_put_constraint()  argument
1068 	if (uncore_box_is_fake(box) || !reg1->alloc)  in nhmex_rbox_put_constraint()
1077 	er = &box->shared_regs[er_idx];  in nhmex_rbox_put_constraint()
1086 static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_rbox_hw_config()  argument
1111 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)  in nhmex_rbox_msr_enable_event()  argument
1119 	port = idx / 6 + box->pmu->pmu_idx * 4;  in nhmex_rbox_msr_enable_event()
1131 			uncore_shared_reg_config(box, 2 + (idx / 6) * 5));  in nhmex_rbox_msr_enable_event()