events/intel/knc.c

13   [PERF_COUNT_HW_CPU_CYCLES]		= 0x002a,
14   [PERF_COUNT_HW_INSTRUCTIONS]		= 0x0016,
15   [PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0028,
16   [PERF_COUNT_HW_CACHE_MISSES]		= 0x0029,
17   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x0012,
18   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x002b,
28 		/* On Xeon Phi event "0" is a valid DATA_READ          */
34 		[ C(RESULT_MISS)   ] = 0x0003,	/* DATA_READ_MISS      */
37 		[ C(RESULT_ACCESS) ] = 0x0001,	/* DATA_WRITE          */
38 		[ C(RESULT_MISS)   ] = 0x0004,	/* DATA_WRITE_MISS     */
41 		[ C(RESULT_ACCESS) ] = 0x0011,	/* L1_DATA_PF1         */
42 		[ C(RESULT_MISS)   ] = 0x001c,	/* L1_DATA_PF1_MISS    */
47 		[ C(RESULT_ACCESS) ] = 0x000c,	/* CODE_READ          */
48 		[ C(RESULT_MISS)   ] = 0x000e,	/* CODE_CACHE_MISS    */
55 		[ C(RESULT_ACCESS) ] = 0x0,
56 		[ C(RESULT_MISS)   ] = 0x0,
61 		[ C(RESULT_ACCESS) ] = 0,
62 		[ C(RESULT_MISS)   ] = 0x10cb,	/* L2_READ_MISS */
65 		[ C(RESULT_ACCESS) ] = 0x10cc,	/* L2_WRITE_HIT */
66 		[ C(RESULT_MISS)   ] = 0,
69 		[ C(RESULT_ACCESS) ] = 0x10fc,	/* L2_DATA_PF2      */
70 		[ C(RESULT_MISS)   ] = 0x10fe,	/* L2_DATA_PF2_MISS */
78 		[ C(RESULT_MISS)   ] = 0x0002,	/* DATA_PAGE_WALK */
81 		[ C(RESULT_ACCESS) ] = 0x0001,	/* DATA_WRITE */
82 		[ C(RESULT_MISS)   ] = 0x0002,	/* DATA_PAGE_WALK */
85 		[ C(RESULT_ACCESS) ] = 0x0,
86 		[ C(RESULT_MISS)   ] = 0x0,
91 		[ C(RESULT_ACCESS) ] = 0x000c,	/* CODE_READ */
92 		[ C(RESULT_MISS)   ] = 0x000d,	/* CODE_PAGE_WALK */
105 		[ C(RESULT_ACCESS) ] = 0x0012,	/* BRANCHES */
106 		[ C(RESULT_MISS)   ] = 0x002b,	/* BRANCHES_MISPREDICTED */
127 	INTEL_EVENT_CONSTRAINT(0xc3, 0x1),	/* HWP_L2HIT */
128 	INTEL_EVENT_CONSTRAINT(0xc4, 0x1),	/* HWP_L2MISS */
129 	INTEL_EVENT_CONSTRAINT(0xc8, 0x1),	/* L2_READ_HIT_E */
130 	INTEL_EVENT_CONSTRAINT(0xc9, 0x1),	/* L2_READ_HIT_M */
131 	INTEL_EVENT_CONSTRAINT(0xca, 0x1),	/* L2_READ_HIT_S */
132 	INTEL_EVENT_CONSTRAINT(0xcb, 0x1),	/* L2_READ_MISS */
133 	INTEL_EVENT_CONSTRAINT(0xcc, 0x1),	/* L2_WRITE_HIT */
134 	INTEL_EVENT_CONSTRAINT(0xce, 0x1),	/* L2_STRONGLY_ORDERED_STREAMING_VSTORES_MISS */
135 	INTEL_EVENT_CONSTRAINT(0xcf, 0x1),	/* L2_WEAKLY_ORDERED_STREAMING_VSTORE_MISS */
136 	INTEL_EVENT_CONSTRAINT(0xd7, 0x1),	/* L2_VICTIM_REQ_WITH_DATA */
137 	INTEL_EVENT_CONSTRAINT(0xe3, 0x1),	/* SNP_HITM_BUNIT */
138 	INTEL_EVENT_CONSTRAINT(0xe6, 0x1),	/* SNP_HIT_L2 */
139 	INTEL_EVENT_CONSTRAINT(0xe7, 0x1),	/* SNP_HITM_L2 */
140 	INTEL_EVENT_CONSTRAINT(0xf1, 0x1),	/* L2_DATA_READ_MISS_CACHE_FILL */
141 	INTEL_EVENT_CONSTRAINT(0xf2, 0x1),	/* L2_DATA_WRITE_MISS_CACHE_FILL */
142 	INTEL_EVENT_CONSTRAINT(0xf6, 0x1),	/* L2_DATA_READ_MISS_MEM_FILL */
143 	INTEL_EVENT_CONSTRAINT(0xf7, 0x1),	/* L2_DATA_WRITE_MISS_MEM_FILL */
144 	INTEL_EVENT_CONSTRAINT(0xfc, 0x1),	/* L2_DATA_PF2 */
145 	INTEL_EVENT_CONSTRAINT(0xfd, 0x1),	/* L2_DATA_PF2_DROP */
146 	INTEL_EVENT_CONSTRAINT(0xfe, 0x1),	/* L2_DATA_PF2_MISS */
147 	INTEL_EVENT_CONSTRAINT(0xff, 0x1),	/* L2_DATA_HIT_INFLIGHT_PF2 */
151 #define MSR_KNC_IA32_PERF_GLOBAL_STATUS		0x0000002d
152 #define MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL	0x0000002e
153 #define MSR_KNC_IA32_PERF_GLOBAL_CTRL		0x0000002f
155 #define KNC_ENABLE_COUNTER0			0x00000001
156 #define KNC_ENABLE_COUNTER1			0x00000002
217 	int handled = 0;  in knc_pmu_handle_irq()
227 		knc_pmu_enable_all(0);  in knc_pmu_handle_irq()
231 	loops = 0;  in knc_pmu_handle_irq()
253 		perf_sample_data_init(&data, 0, event->hw.last_period);  in knc_pmu_handle_irq()
256 			x86_pmu_stop(event, 0);  in knc_pmu_handle_irq()
269 		knc_pmu_enable_all(0);  in knc_pmu_handle_irq()
275 PMU_FORMAT_ATTR(event,	"config:0-7"	);
305 	.version		= 0,
321 	return 0;  in knc_pmu_init()