158 	u32 shift, bank, cntr;  in get_next_avail_iommu_bnk_cntr()  local
165 		for (cntr = 0; cntr < max_cntrs; cntr++) {  in get_next_avail_iommu_bnk_cntr()
166 			shift = bank + (bank*3) + cntr;  in get_next_avail_iommu_bnk_cntr()
172 				event->hw.iommu_cntr = cntr;  in get_next_avail_iommu_bnk_cntr()
185 					u8 bank, u8 cntr)  in clear_avail_iommu_bnk_cntr()  argument
194 	if ((bank > max_banks) || (cntr > max_cntrs))  in clear_avail_iommu_bnk_cntr()
197 	shift = bank + cntr + (bank*3);  in clear_avail_iommu_bnk_cntr()
242 	u8 cntr = hwc->iommu_cntr;  in perf_iommu_enable_event()  local
246 	amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, &reg);  in perf_iommu_enable_event()
252 	amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, &reg);  in perf_iommu_enable_event()
258 	amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, &reg);  in perf_iommu_enable_event()
264 	amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, &reg);  in perf_iommu_enable_event()