21 static u32 ibs_caps;  variable
362 		if (ibs_caps & IBS_CAPS_OPCNTEXT)  in get_ibs_op_count()
364 	} else if (ibs_caps & IBS_CAPS_RDWROPCNT) {  in get_ibs_op_count()
436 	if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {  in perf_ibs_start()
575 	return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0;  in zen4_ibs_extensions_is_visible()
625 	return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0;  in cnt_ctl_is_visible()
725 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_data_src()
797 	if (ibs_caps & IBS_CAPS_ZEN4) {  in perf_ibs_get_mem_lvl()
880 	if (ibs_caps & IBS_CAPS_ZEN4) {  in perf_ibs_get_mem_snoop()
1062 	ibs_data.caps = ibs_caps;  in perf_ibs_handle_irq()
1065 	check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));  in perf_ibs_handle_irq()
1083 			if (ibs_caps & IBS_CAPS_BRNTRGT) {  in perf_ibs_handle_irq()
1087 			if (ibs_caps & IBS_CAPS_OPDATA4) {  in perf_ibs_handle_irq()
1092 		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {  in perf_ibs_handle_irq()
1138 			if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_ibs_handle_irq()
1142 			if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))  in perf_ibs_handle_irq()
1205 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_fetch_init()
1216 	if (ibs_caps & IBS_CAPS_OPCNT)  in perf_ibs_op_init()
1219 	if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_ibs_op_init()
1225 	if (ibs_caps & IBS_CAPS_ZEN4)  in perf_ibs_op_init()
1250 	pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);  in perf_event_ibs_init()
1299 	return ibs_caps;  in get_ibs_caps()
1528 	ibs_caps = caps;  in amd_ibs_init()