107 { return !(pmd_val(pmd) & 0xFFFFFFF); }  in srmmu_pmd_none()
121 #define MSI_MBUS_ARBEN	0xe0001008	/* MBus Arbiter Enable register */
126 #define MSI_ASYNC_MODE  0x80000000	/* Operate the MSI asynchronously */
130 	__asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"  in msi_set_sync()
132 			      "sta %%g3, [%0] %1\n\t" : :  in msi_set_sync()
154 		printk(KERN_ERR "Size 0x%x too small for nocache request\n",  in __srmmu_get_nocache()
159 		printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",  in __srmmu_get_nocache()
186 		memset(tmp, 0, size);  in srmmu_get_nocache()
198 		printk("Vaddr %lx is smaller than nocache base 0x%lx\n",  in srmmu_free_nocache()
203 		printk("Vaddr %lx is bigger than nocache end 0x%lx\n",  in srmmu_free_nocache()
208 		printk("Size 0x%x is not a power of 2\n", size);  in srmmu_free_nocache()
212 		printk("Size 0x%x is too small\n", size);  in srmmu_free_nocache()
216 		printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);  in srmmu_free_nocache()
232 	unsigned long total = 0;  in probe_memory()
235 	for (i = 0; sp_banks[i].num_bytes; i++)  in probe_memory()
283 		panic("%s: Failed to allocate %lu bytes align=0x%x\n",  in srmmu_nocache_init()
285 	memset(srmmu_nocache_pool, 0, srmmu_nocache_size);  in srmmu_nocache_init()
296 	memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);  in srmmu_nocache_init()
332 		pgd_t *init = pgd_offset_k(0);  in get_pgd_fast()
333 		memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));  in get_pgd_fast()
459 	for (ctx = 0; ctx < numctx; ctx++) {  in sparc_context_init()
468 	for (ctx = 0; ctx < numctx; ctx++)  in sparc_context_init()
525 	while (len != 0) {  in srmmu_mapiorange()
555 	while (len != 0) {  in srmmu_unmapiorange()
592 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
605 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
614 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
698 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);  in srmmu_early_allocate_ptable_skeleton()
706 			memset(__nocache_fix(ptep), 0, PTE_SIZE);  in srmmu_early_allocate_ptable_skeleton()
709 		if (start > (0xffffffffUL - PMD_SIZE))  in srmmu_early_allocate_ptable_skeleton()
732 			memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);  in srmmu_allocate_ptable_skeleton()
741 			memset(ptep, 0, PTE_SIZE);  in srmmu_allocate_ptable_skeleton()
744 		if (start > (0xffffffffUL - PMD_SIZE))  in srmmu_allocate_ptable_skeleton()
758 		__asm__ __volatile__("lda [%1] %2, %0\n\t" :  in srmmu_probe()
760 				     "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));  in srmmu_probe()
782 	int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */  in srmmu_inherit_prom_mappings()
785 		if (start == 0)  in srmmu_inherit_prom_mappings()
787 		if (start == 0xfef00000)  in srmmu_inherit_prom_mappings()
797 		what = 0;  in srmmu_inherit_prom_mappings()
823 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);  in srmmu_inherit_prom_mappings()
836 			memset(__nocache_fix(ptep), 0, PTE_SIZE);  in srmmu_inherit_prom_mappings()
884 	if (phys_base > 0) {  in map_kernel()
888 	for (i = 0; sp_banks[i].num_bytes != 0; i++) {  in map_kernel()
915 		num_contexts = 0;  in srmmu_paging_init()
916 		while (cpunode != 0) {  in srmmu_paging_init()
919 				num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);  in srmmu_paging_init()
931 	pages_avail = 0;  in srmmu_paging_init()
936 	srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));  in srmmu_paging_init()
943 	for (i = 0; i < num_contexts; i++)  in srmmu_paging_init()
976 		unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };  in srmmu_paging_init()
1002 	return 0;  in init_new_context()
1033 	int cpu = 0;  in init_vac_layout()
1034 	unsigned long max_size = 0;  in init_vac_layout()
1035 	unsigned long min_line_size = 0x10000000;  in init_vac_layout()
1039 	while ((nd = prom_getsibling(nd)) != 0) {  in init_vac_layout()
1068 	if (nd == 0) {  in init_vac_layout()
1093 #if 0 /* XXX I think this is bad news... -DaveM */  in poke_hypersparc()
1169 #define SWIFT_MASKID_ADDR  0x10003018
1174 	__asm__ __volatile__("lda [%1] %2, %0\n\t"  in init_swift()
1175 			     "srl %0, 0x18, %0\n\t" :  in init_swift()
1180 	case 0x11:  in init_swift()
1181 	case 0x20:  in init_swift()
1182 	case 0x23:  in init_swift()
1183 	case 0x30:  in init_swift()
1204 	case 0x25:  in init_swift()
1205 	case 0x31:  in init_swift()
1220 	flush_page_for_dma_global = 0;  in init_swift()
1340 	case 0: /* No SE cache */  in poke_turbosparc()
1511 		viking_mxcc_present = 0;  in init_viking()
1525 		flush_page_for_dma_global = 0;  in init_viking()
1550 	hwbug_bitmask = 0;  in get_srmmu_type()
1553 	mod_typ = (mreg & 0xf0000000) >> 28;  in get_srmmu_type()
1554 	mod_rev = (mreg & 0x0f000000) >> 24;  in get_srmmu_type()
1555 	psr_typ = (psr >> 28) & 0xf;  in get_srmmu_type()
1556 	psr_vers = (psr >> 24) & 0xf;  in get_srmmu_type()
1571 		case 0:  in get_srmmu_type()
1590 	if (psr_typ == 0 && psr_vers == 5) {  in get_srmmu_type()
1596 	if (psr_typ == 0 && psr_vers == 4) {  in get_srmmu_type()
1602 		while ((cpunode = prom_getsibling(cpunode)) != 0) {  in get_srmmu_type()
1620 	   ((psr_vers == 0) ||  in get_srmmu_type()
1621 	    ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {  in get_srmmu_type()