Lines Matching refs:sparc_pmu

157 struct sparc_pmu {  struct
321 static const struct sparc_pmu ultra3_pmu = {
459 static const struct sparc_pmu niagara1_pmu = {
594 static const struct sparc_pmu niagara2_pmu = {
751 static const struct sparc_pmu niagara4_pmu = {
781 static const struct sparc_pmu sparc_m7_pmu = {
804 static const struct sparc_pmu *sparc_pmu __read_mostly;
809 event_id <<= sparc_pmu->upper_shift; in event_encoding()
811 event_id <<= sparc_pmu->lower_shift; in event_encoding()
817 return event_encoding(sparc_pmu->event_mask, idx); in mask_for_index()
823 sparc_pmu->upper_nop : in nop_for_index()
824 sparc_pmu->lower_nop, idx); in nop_for_index()
832 if (sparc_pmu->num_pcrs > 1) in sparc_pmu_enable_event()
852 if (sparc_pmu->num_pcrs > 1) in sparc_pmu_disable_event()
872 new_raw_count = sparc_pmu->read_pmc(idx); in sparc_perf_event_update()
916 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff); in sparc_perf_event_set_period()
1022 if (sparc_pmu->num_pcrs == 1) { in update_pcrs_for_enable()
1043 for (i = 0; i < sparc_pmu->num_pcrs; i++) in sparc_pmu_enable()
1058 for (i = 0; i < sparc_pmu->num_pcrs; i++) { in sparc_pmu_disable()
1061 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit | in sparc_pmu_disable()
1062 sparc_pmu->hv_bit | sparc_pmu->irq_bit); in sparc_pmu_disable()
1167 for (i = 0; i < sparc_pmu->num_pcrs; i++) in perf_stop_nmi_watchdog()
1201 if (!sparc_pmu->cache_map) in sparc_map_cache_event()
1216 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); in sparc_map_cache_event()
1254 if (n_ev > sparc_pmu->max_hw_events) in sparc_check_constraints()
1257 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { in sparc_check_constraints()
1320 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) in check_excludes()
1381 if (n0 >= sparc_pmu->max_hw_events) in sparc_pmu_add()
1434 if (attr->config >= sparc_pmu->max_events) in sparc_pmu_event_init()
1436 pmap = sparc_pmu->event_map(attr->config); in sparc_pmu_event_init()
1465 hwc->config_base = sparc_pmu->irq_bit; in sparc_pmu_event_init()
1467 hwc->config_base |= sparc_pmu->user_bit; in sparc_pmu_event_init()
1469 hwc->config_base |= sparc_pmu->priv_bit; in sparc_pmu_event_init()
1471 hwc->config_base |= sparc_pmu->hv_bit; in sparc_pmu_event_init()
1476 sparc_pmu->max_hw_events - 1, in sparc_pmu_event_init()
1555 if (!sparc_pmu) in sparc_pmu_commit_txn()
1595 if (!sparc_pmu) in perf_event_print_debug()
1603 for (i = 0; i < sparc_pmu->num_pcrs; i++) in perf_event_print_debug()
1606 for (i = 0; i < sparc_pmu->num_pic_regs; i++) in perf_event_print_debug()
1648 if (sparc_pmu->irq_bit && in perf_event_nmi_handler()
1649 sparc_pmu->num_pcrs == 1) in perf_event_nmi_handler()
1658 if (sparc_pmu->irq_bit && in perf_event_nmi_handler()
1659 sparc_pmu->num_pcrs > 1) in perf_event_nmi_handler()
1692 sparc_pmu = &ultra3_pmu; in supported_pmu()
1696 sparc_pmu = &niagara1_pmu; in supported_pmu()
1701 sparc_pmu = &niagara2_pmu; in supported_pmu()
1706 sparc_pmu = &niagara4_pmu; in supported_pmu()
1710 sparc_pmu = &sparc_m7_pmu; in supported_pmu()