Lines Matching +full:- +full:1 +full:ul
1 // SPDX-License-Identifier: GPL-2.0
53 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
54 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
55 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
56 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
62 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
69 * 32 24 23 16 15 11 10 8 7 2 1 0
70 * ---------------------------------------------------------
72 * ---------------------------------------------------------
74 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
87 bus -= pbm->pci_first_busno; in schizo_pci_config_mkaddr()
109 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
110 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
111 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
131 struct strbuf *strbuf = &pbm->stc; in __schizo_check_stc_error_pbm()
132 unsigned long regbase = pbm->pbm_regs; in __schizo_check_stc_error_pbm()
146 * of the line tag valid bits before re-enabling in __schizo_check_stc_error_pbm()
152 control = upa_readq(strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
154 strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
158 val = upa_readq(err_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
159 upa_writeq(0UL, err_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
163 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
164 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
165 upa_writeq(0UL, tag_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
166 upa_writeq(0UL, line_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
170 upa_writeq(control, strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
183 pbm->name, in __schizo_check_stc_error_pbm()
185 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, in __schizo_check_stc_error_pbm()
186 (errval & SCHIZO_STCERR_READ) ? 1 : 0); in __schizo_check_stc_error_pbm()
193 pbm->name, in __schizo_check_stc_error_pbm()
195 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), in __schizo_check_stc_error_pbm()
197 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), in __schizo_check_stc_error_pbm()
198 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); in __schizo_check_stc_error_pbm()
200 /* XXX Should spit out per-bank error information... -DaveM */ in __schizo_check_stc_error_pbm()
203 pbm->name, in __schizo_check_stc_error_pbm()
205 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), in __schizo_check_stc_error_pbm()
206 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), in __schizo_check_stc_error_pbm()
207 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), in __schizo_check_stc_error_pbm()
208 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), in __schizo_check_stc_error_pbm()
209 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), in __schizo_check_stc_error_pbm()
210 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); in __schizo_check_stc_error_pbm()
217 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
239 struct iommu *iommu = pbm->iommu; in schizo_check_iommu_error_pbm()
246 spin_lock_irqsave(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
247 control = upa_readq(iommu->iommu_control); in schizo_check_iommu_error_pbm()
254 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
256 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { in schizo_check_iommu_error_pbm()
260 case 1: in schizo_check_iommu_error_pbm()
272 pbm->name, type_string); in schizo_check_iommu_error_pbm()
285 iommu->iommu_control); in schizo_check_iommu_error_pbm()
287 base = pbm->pbm_regs; in schizo_check_iommu_error_pbm()
291 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); in schizo_check_iommu_error_pbm()
293 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); in schizo_check_iommu_error_pbm()
296 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); in schizo_check_iommu_error_pbm()
297 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); in schizo_check_iommu_error_pbm()
301 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
311 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { in schizo_check_iommu_error_pbm()
315 case 1: in schizo_check_iommu_error_pbm()
328 pbm->name, i, type_string, in schizo_check_iommu_error_pbm()
329 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), in schizo_check_iommu_error_pbm()
330 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), in schizo_check_iommu_error_pbm()
331 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), in schizo_check_iommu_error_pbm()
335 pbm->name, i, in schizo_check_iommu_error_pbm()
336 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), in schizo_check_iommu_error_pbm()
337 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), in schizo_check_iommu_error_pbm()
341 if (pbm->stc.strbuf_enabled) in schizo_check_iommu_error_pbm()
343 spin_unlock_irqrestore(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
350 if (pbm->sibling) in schizo_check_iommu_error()
351 schizo_check_iommu_error_pbm(pbm->sibling, type); in schizo_check_iommu_error()
376 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; in schizo_ue_intr()
377 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; in schizo_ue_intr()
386 * the hardware and we must re-read to get a clean value. in schizo_ue_intr()
391 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); in schizo_ue_intr()
403 pbm->name, in schizo_ue_intr()
411 pbm->name, in schizo_ue_intr()
412 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, in schizo_ue_intr()
413 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, in schizo_ue_intr()
414 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); in schizo_ue_intr()
416 pbm->name, in schizo_ue_intr()
417 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, in schizo_ue_intr()
418 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, in schizo_ue_intr()
419 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, in schizo_ue_intr()
420 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, in schizo_ue_intr()
421 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); in schizo_ue_intr()
422 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); in schizo_ue_intr()
423 printk("%s: UE Secondary errors [", pbm->name); in schizo_ue_intr()
464 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; in schizo_ce_intr()
465 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; in schizo_ce_intr()
474 * the hardware and we must re-read to get a clean value. in schizo_ce_intr()
479 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); in schizo_ce_intr()
491 pbm->name, in schizo_ce_intr()
500 * XXX UDB CE trap handler does... -DaveM in schizo_ce_intr()
503 pbm->name, in schizo_ce_intr()
504 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, in schizo_ce_intr()
505 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, in schizo_ce_intr()
506 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); in schizo_ce_intr()
508 pbm->name, in schizo_ce_intr()
509 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, in schizo_ce_intr()
510 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, in schizo_ce_intr()
511 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, in schizo_ce_intr()
512 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, in schizo_ce_intr()
513 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); in schizo_ce_intr()
514 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); in schizo_ce_intr()
515 printk("%s: CE Secondary errors [", pbm->name); in schizo_ce_intr()
554 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
555 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
556 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
557 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
558 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
559 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
560 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
561 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
562 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
563 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
564 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
565 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
566 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
567 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
568 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
569 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
570 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
571 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
572 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
573 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
574 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
575 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
576 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
577 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
578 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
579 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
580 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
588 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; in schizo_pcierr_intr_other()
604 pbm->name); in schizo_pcierr_intr_other()
607 pbm->name); in schizo_pcierr_intr_other()
610 pbm->name); in schizo_pcierr_intr_other()
613 pbm->name); in schizo_pcierr_intr_other()
616 pbm->name); in schizo_pcierr_intr_other()
619 pbm->name); in schizo_pcierr_intr_other()
622 pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat); in schizo_pcierr_intr_other()
629 pbm->name, stat); in schizo_pcierr_intr_other()
630 pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff); in schizo_pcierr_intr_other()
643 base = pbm->pbm_regs; in schizo_pcierr_intr()
666 pbm->name, in schizo_pcierr_intr()
680 pbm->name, in schizo_pcierr_intr()
681 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, in schizo_pcierr_intr()
682 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, in schizo_pcierr_intr()
690 pbm->name, afar); in schizo_pcierr_intr()
692 pbm->name); in schizo_pcierr_intr()
733 pci_scan_for_target_abort(pbm, pbm->pci_bus); in schizo_pcierr_intr()
736 pci_scan_for_master_abort(pbm, pbm->pci_bus); in schizo_pcierr_intr()
746 pci_scan_for_parity_error(pbm, pbm->pci_bus); in schizo_pcierr_intr()
795 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); in schizo_safarierr_intr()
797 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); in schizo_safarierr_intr()
801 pbm->name, errlog); in schizo_safarierr_intr()
807 pbm->name); in schizo_safarierr_intr()
828 if (pbm->ino_bitmap & (1UL << ino)) in pbm_routes_this_ino()
829 return 1; in pbm_routes_this_ino()
850 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); in tomatillo_register_error_handlers()
856 * 1: UE ERR in tomatillo_register_error_handlers()
863 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, in tomatillo_register_error_handlers()
867 "err=%d\n", pbm->name, err); in tomatillo_register_error_handlers()
870 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, in tomatillo_register_error_handlers()
874 "err=%d\n", pbm->name, err); in tomatillo_register_error_handlers()
878 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, in tomatillo_register_error_handlers()
881 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, in tomatillo_register_error_handlers()
886 "err=%d\n", pbm->name, err); in tomatillo_register_error_handlers()
889 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, in tomatillo_register_error_handlers()
893 "err=%d\n", pbm->name, err); in tomatillo_register_error_handlers()
899 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); in tomatillo_register_error_handlers()
912 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); in tomatillo_register_error_handlers()
915 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); in tomatillo_register_error_handlers()
924 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); in tomatillo_register_error_handlers()
937 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); in tomatillo_register_error_handlers()
940 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); in tomatillo_register_error_handlers()
945 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); in schizo_register_error_handlers()
951 * 1: UE ERR in schizo_register_error_handlers()
958 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, in schizo_register_error_handlers()
962 "err=%d\n", pbm->name, err); in schizo_register_error_handlers()
965 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, in schizo_register_error_handlers()
969 "err=%d\n", pbm->name, err); in schizo_register_error_handlers()
973 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, in schizo_register_error_handlers()
976 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, in schizo_register_error_handlers()
981 "err=%d\n", pbm->name, err); in schizo_register_error_handlers()
984 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, in schizo_register_error_handlers()
988 "err=%d\n", pbm->name, err); in schizo_register_error_handlers()
994 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); in schizo_register_error_handlers()
1010 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); in schizo_register_error_handlers()
1013 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); in schizo_register_error_handlers()
1021 pbm->pbm_regs + SCHIZO_PCI_AFSR); in schizo_register_error_handlers()
1036 #if 1 in schizo_register_error_handlers()
1038 * XXX Sun is shipping. The behavior on a 2-cpu in schizo_register_error_handlers()
1042 * XXX ignore them for now. -DaveM in schizo_register_error_handlers()
1049 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); in schizo_register_error_handlers()
1056 /* Set cache-line size to 64 bytes, this is actually in pbm_config_busmastering()
1059 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, in pbm_config_busmastering()
1064 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, in pbm_config_busmastering()
1072 pbm->is_66mhz_capable = in schizo_scan_bus()
1073 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) in schizo_scan_bus()
1076 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); in schizo_scan_bus()
1078 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) in schizo_scan_bus()
1092 unsigned long base = pbm->pbm_regs; in schizo_pbm_strbuf_init()
1095 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { in schizo_pbm_strbuf_init()
1101 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; in schizo_pbm_strbuf_init()
1102 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; in schizo_pbm_strbuf_init()
1103 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; in schizo_pbm_strbuf_init()
1104 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; in schizo_pbm_strbuf_init()
1105 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; in schizo_pbm_strbuf_init()
1107 pbm->stc.strbuf_flushflag = (volatile unsigned long *) in schizo_pbm_strbuf_init()
1108 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) in schizo_pbm_strbuf_init()
1109 + 63UL) in schizo_pbm_strbuf_init()
1110 & ~63UL); in schizo_pbm_strbuf_init()
1111 pbm->stc.strbuf_flushflag_pa = (unsigned long) in schizo_pbm_strbuf_init()
1112 __pa(pbm->stc.strbuf_flushflag); in schizo_pbm_strbuf_init()
1115 * streaming buffer and leave the rerun-disable in schizo_pbm_strbuf_init()
1118 control = upa_readq(pbm->stc.strbuf_control); in schizo_pbm_strbuf_init()
1123 upa_writeq(control, pbm->stc.strbuf_control); in schizo_pbm_strbuf_init()
1125 pbm->stc.strbuf_enabled = 1; in schizo_pbm_strbuf_init()
1137 struct iommu *iommu = pbm->iommu; in schizo_pbm_iommu_init()
1143 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); in schizo_pbm_iommu_init()
1148 switch (vdma[1]) { in schizo_pbm_iommu_init()
1165 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); in schizo_pbm_iommu_init()
1166 return -EINVAL; in schizo_pbm_iommu_init()
1170 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; in schizo_pbm_iommu_init()
1171 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; in schizo_pbm_iommu_init()
1172 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; in schizo_pbm_iommu_init()
1173 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); in schizo_pbm_iommu_init()
1174 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; in schizo_pbm_iommu_init()
1179 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; in schizo_pbm_iommu_init()
1184 control = upa_readq(iommu->iommu_control); in schizo_pbm_iommu_init()
1186 upa_writeq(control, iommu->iommu_control); in schizo_pbm_iommu_init()
1191 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); in schizo_pbm_iommu_init()
1192 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); in schizo_pbm_iommu_init()
1195 /* Leave diag mode enabled for full-flushing done in schizo_pbm_iommu_init()
1199 pbm->numa_node); in schizo_pbm_iommu_init()
1205 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); in schizo_pbm_iommu_init()
1207 control = upa_readq(iommu->iommu_control); in schizo_pbm_iommu_init()
1219 upa_writeq(control, iommu->iommu_control); in schizo_pbm_iommu_init()
1228 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1229 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1230 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1231 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1232 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1233 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1234 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1235 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1236 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo)…
1244 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1246 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1248 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1250 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1262 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); in schizo_pbm_hw_init()
1264 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); in schizo_pbm_hw_init()
1269 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && in schizo_pbm_hw_init()
1270 pbm->chip_version >= 0x2) in schizo_pbm_hw_init()
1273 if (!of_property_read_bool(pbm->op->dev.of_node, "no-bus-parking")) in schizo_pbm_hw_init()
1278 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && in schizo_pbm_hw_init()
1279 pbm->chip_version <= 0x1) in schizo_pbm_hw_init()
1284 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) in schizo_pbm_hw_init()
1289 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); in schizo_pbm_hw_init()
1291 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); in schizo_pbm_hw_init()
1295 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); in schizo_pbm_hw_init()
1297 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { in schizo_pbm_hw_init()
1302 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | in schizo_pbm_hw_init()
1307 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); in schizo_pbm_hw_init()
1316 struct device_node *dp = op->dev.of_node; in schizo_pbm_init()
1336 * 1) PBM controller regs in schizo_pbm_init()
1337 * 2) Schizo front-end controller regs (same for both PBMs) in schizo_pbm_init()
1341 * 1) PBM controller regs in schizo_pbm_init()
1342 * 2) Tomatillo front-end controller regs in schizo_pbm_init()
1348 pbm->next = pci_pbm_root; in schizo_pbm_init()
1351 pbm->numa_node = NUMA_NO_NODE; in schizo_pbm_init()
1353 pbm->pci_ops = &sun4u_pci_ops; in schizo_pbm_init()
1354 pbm->config_space_reg_bits = 8; in schizo_pbm_init()
1356 pbm->index = pci_num_pbms++; in schizo_pbm_init()
1358 pbm->portid = portid; in schizo_pbm_init()
1359 pbm->op = op; in schizo_pbm_init()
1361 pbm->chip_type = chip_type; in schizo_pbm_init()
1362 pbm->chip_version = of_getintprop_default(dp, "version#", 0); in schizo_pbm_init()
1363 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); in schizo_pbm_init()
1365 pbm->pbm_regs = regs[0].phys_addr; in schizo_pbm_init()
1366 pbm->controller_regs = regs[1].phys_addr - 0x10000UL; in schizo_pbm_init()
1369 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; in schizo_pbm_init()
1371 pbm->name = dp->full_name; in schizo_pbm_init()
1374 pbm->name, chipset_name, in schizo_pbm_init()
1375 pbm->chip_version, pbm->chip_revision); in schizo_pbm_init()
1389 schizo_scan_bus(pbm, &op->dev); in schizo_pbm_init()
1397 if (x == (y ^ 1)) in portid_compare()
1398 return 1; in portid_compare()
1408 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { in schizo_find_sibling()
1409 if (portid_compare(pbm->portid, portid, chip_type)) in schizo_find_sibling()
1417 struct device_node *dp = op->dev.of_node; in __schizo_init()
1425 err = -ENOMEM; in __schizo_init()
1432 pbm->sibling = schizo_find_sibling(portid, chip_type); in __schizo_init()
1440 pbm->iommu = iommu; in __schizo_init()
1445 if (pbm->sibling) in __schizo_init()
1446 pbm->sibling->sibling = pbm; in __schizo_init()
1448 dev_set_drvdata(&op->dev, pbm); in __schizo_init()
1453 kfree(pbm->iommu); in __schizo_init()
1467 match = of_match_device(schizo_match, &op->dev); in schizo_probe()
1469 return -EINVAL; in schizo_probe()
1470 return __schizo_init(op, (unsigned long)match->data); in schizo_probe()