95 #define REGSTORE(a, v)	(__raw_writel(cpu_to_be32(v), &(a)))  macro
255 	REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |  in grpci2_cfg_r32()
260 	REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));  in grpci2_cfg_r32()
325 	REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |  in grpci2_cfg_w32()
330 	REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));  in grpci2_cfg_w32()
465 	REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));  in grpci2_mask_irq()
480 	REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));  in grpci2_unmask_irq()
577 		REGSTORE(regs->ctrl, CTRL_RESET);  in grpci2_hw_init()
580 	REGSTORE(regs->ctrl, 0);  in grpci2_hw_init()
581 	REGSTORE(regs->sts_cap, ~0); /* Clear Status */  in grpci2_hw_init()
582 	REGSTORE(regs->dma_ctrl, 0);  in grpci2_hw_init()
583 	REGSTORE(regs->dma_bdbase, 0);  in grpci2_hw_init()
586 	REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);  in grpci2_hw_init()
592 		REGSTORE(regs->ahbmst_map[i], priv->pci_area);  in grpci2_hw_init()
648 	REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);  in grpci2_hw_init()
681 	REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);  in grpci2_err_interrupt()
853 		REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));  in grpci2_of_probe()
868 	REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);  in grpci2_of_probe()