Lines Matching refs:EBDMA_CSR
17 #define EBDMA_CSR 0x00UL /* Control/Status */ macro
55 writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR); in __ebus_dma_reset()
62 val = readl(p->regs + EBDMA_CSR); in __ebus_dma_reset()
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
136 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
138 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
142 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
144 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
163 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_unregister()
166 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_unregister()
186 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_request()
223 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_prepare()
247 orig_csr = csr = readl(p->regs + EBDMA_CSR); in ebus_dma_enable()
254 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_enable()