1 // SPDX-License-Identifier: GPL-2.0-only
2 /* chmc.c: Driver for UltraSPARC-III memory controller.
34 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
49 /* OBP memory-layout property format. */
58 	/* One max 8-byte string label per DIMM.  Usually
148 	/* One max 8-byte string label per DIMM.  Usually
199 #define SYNDROME_MIN	-1
210 		syndrome_code -= (128 - 7);  in syndrome_to_qword_code()
212 		syndrome_code -= (128 + 9 - 4);  in syndrome_to_qword_code()
214 		syndrome_code -= (128 + 9 + 3);  in syndrome_to_qword_code()
219  * on Safari and JBUS.  A 64-bit line comes over in 1 or more quadword
224 #define L2_LINE_ADDR_MSK	(L2_LINE_SIZE - 1)
228 #define SAFARI_LAST_BIT		(576 - 1)
229 #define JBUS_LAST_BIT		(144 - 1)
246 		offset_inverse = (JBUS_LAST_BIT - cache_line_offset);  in get_pin_and_dimm_str()
248 		map_val = p->map.dimm_map[dimm_map_index];  in get_pin_and_dimm_str()
249 		map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1);  in get_pin_and_dimm_str()
250 		*dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];  in get_pin_and_dimm_str()
251 		*pin_p = p->map.pin_map[cache_line_offset];  in get_pin_and_dimm_str()
258 		if (p->symmetric)  in get_pin_and_dimm_str()
259 			mp = &p->map[0];  in get_pin_and_dimm_str()
261 			mp = &p->map[1];  in get_pin_and_dimm_str()
264 		cache_line_offset = ((3 - qword) * QW_BITS) + qword_code;  in get_pin_and_dimm_str()
265 		offset_inverse = (SAFARI_LAST_BIT - cache_line_offset);  in get_pin_and_dimm_str()
267 		map_val = mp->dimm_map[dimm_map_index];  in get_pin_and_dimm_str()
268 		map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3);  in get_pin_and_dimm_str()
269 		*dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];  in get_pin_and_dimm_str()
270 		*pin_p = mp->pin_map[cache_line_offset];  in get_pin_and_dimm_str()
281 		for (i = 0; i < p->num_dimm_groups; i++) {  in jbusmc_find_dimm_group()
282 			struct jbusmc_dimm_group *dp = &p->dimm_groups[i];  in jbusmc_find_dimm_group()
284 			if (phys_addr < dp->base_addr ||  in jbusmc_find_dimm_group()
285 			    (dp->base_addr + dp->size) <= phys_addr)  in jbusmc_find_dimm_group()
313 	p = dp->controller;  in jbusmc_print_dimm()
314 	prop = &p->layout;  in jbusmc_print_dimm()
316 	first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP;  in jbusmc_print_dimm()
328 		/* Multi-bit error, we just dump out all the  in jbusmc_print_dimm()
333 				prop->dimm_labels[first_dimm + dimm]);  in jbusmc_print_dimm()
355 		this_base = ent->phys_addr;  in jbusmc_dimm_group_size()
356 		this_end = this_base + ent->reg_size;  in jbusmc_dimm_group_size()
365 	return max_seen - base;  in jbusmc_dimm_group_size()
373 	struct jbusmc_dimm_group *dp = &p->dimm_groups[index];  in jbusmc_construct_one_dimm_group()
375 	dp->controller = p;  in jbusmc_construct_one_dimm_group()
376 	dp->index = index;  in jbusmc_construct_one_dimm_group()
378 	dp->base_addr  = (p->portid * (64UL * 1024 * 1024 * 1024));  in jbusmc_construct_one_dimm_group()
379 	dp->base_addr += (index * (8UL * 1024 * 1024 * 1024));  in jbusmc_construct_one_dimm_group()
380 	dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs);  in jbusmc_construct_one_dimm_group()
387 	if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) {  in jbusmc_construct_dimm_groups()
389 		p->num_dimm_groups++;  in jbusmc_construct_dimm_groups()
391 	if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) {  in jbusmc_construct_dimm_groups()
393 		p->num_dimm_groups++;  in jbusmc_construct_dimm_groups()
406 	err = -ENODEV;  in jbusmc_probe()
419 	err = -ENOMEM;  in jbusmc_probe()
426 	INIT_LIST_HEAD(&p->list);  in jbusmc_probe()
428 	err = -ENODEV;  in jbusmc_probe()
429 	prop = of_get_property(op->dev.of_node, "portid", &len);  in jbusmc_probe()
435 	p->portid = *prop;  in jbusmc_probe()
437 	prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len);  in jbusmc_probe()
443 	p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1];  in jbusmc_probe()
445 	err = -ENOMEM;  in jbusmc_probe()
446 	p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc");  in jbusmc_probe()
447 	if (!p->regs) {  in jbusmc_probe()
452 	err = -ENODEV;  in jbusmc_probe()
453 	ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len);  in jbusmc_probe()
458 	if (p->layout_len > sizeof(p->layout)) {  in jbusmc_probe()
459 		printk(KERN_ERR PFX "Unexpected memory-layout size %d\n",  in jbusmc_probe()
460 		       p->layout_len);  in jbusmc_probe()
463 	memcpy(&p->layout, ml, p->layout_len);  in jbusmc_probe()
467 	mc_list_add(&p->list);  in jbusmc_probe()
469 	printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %pOF\n",  in jbusmc_probe()
470 	       op->dev.of_node);  in jbusmc_probe()
472 	dev_set_drvdata(&op->dev, p);  in jbusmc_probe()
480 	of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);  in jbusmc_probe()
494 	if (bp->valid == 0)  in chmc_bank_match()
498 	upper_bits ^= bp->um;		/* What bits are different? */  in chmc_bank_match()
500 	upper_bits |= bp->uk;		/* What bits don't matter for matching? */  in chmc_bank_match()
507 	lower_bits ^= bp->lm;		/* What bits are different? */  in chmc_bank_match()
509 	lower_bits |= bp->lk;		/* What bits don't matter for matching? */  in chmc_bank_match()
530 			bp = &p->logical_banks[bank_no];  in chmc_find_bank()
559 	prop = &bp->p->layout_prop;  in chmc_print_dimm()
560 	bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);  in chmc_print_dimm()
561 	first_dimm  = (bank_in_controller & (CHMCTRL_NDGRPS - 1));  in chmc_print_dimm()
574 		/* Multi-bit error, we just dump out all the  in chmc_print_dimm()
579 				prop->dimm_labels[first_dimm + dimm]);  in chmc_print_dimm()
588  * the code is executing, you must use special ASI load/store else
599 	if (p->portid == this_cpu) {  in chmc_read_mcreg()
606 				     : "r" (p->regs + offset),  in chmc_read_mcreg()
618 	if (p->portid == smp_processor_id()) {
625 				         "r" (p->regs + offset),
633 	struct chmc_bank_info *bp = &p->logical_banks[which_bank];  in chmc_interpret_one_decode_reg()
635 	bp->p = p;  in chmc_interpret_one_decode_reg()
636 	bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;  in chmc_interpret_one_decode_reg()
637 	bp->raw_reg = val;  in chmc_interpret_one_decode_reg()
638 	bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;  in chmc_interpret_one_decode_reg()
639 	bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;  in chmc_interpret_one_decode_reg()
640 	bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;  in chmc_interpret_one_decode_reg()
641 	bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;  in chmc_interpret_one_decode_reg()
642 	bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;  in chmc_interpret_one_decode_reg()
644 	bp->base  =  (bp->um);  in chmc_interpret_one_decode_reg()
645 	bp->base &= ~(bp->uk);  in chmc_interpret_one_decode_reg()
646 	bp->base <<= PA_UPPER_BITS_SHIFT;  in chmc_interpret_one_decode_reg()
648 	switch(bp->lk) {  in chmc_interpret_one_decode_reg()
651 		bp->interleave = 1;  in chmc_interpret_one_decode_reg()
655 		bp->interleave = 2;  in chmc_interpret_one_decode_reg()
659 		bp->interleave = 4;  in chmc_interpret_one_decode_reg()
663 		bp->interleave = 8;  in chmc_interpret_one_decode_reg()
667 		bp->interleave = 16;  in chmc_interpret_one_decode_reg()
674 	bp->size = (((unsigned long)bp->uk &  in chmc_interpret_one_decode_reg()
675 		     ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;  in chmc_interpret_one_decode_reg()
676 	bp->size /= bp->interleave;  in chmc_interpret_one_decode_reg()
681 	if (p->layout_size == 0)  in chmc_fetch_decode_regs()
696 	struct device_node *dp = op->dev.of_node;  in chmc_probe()
703 	err = -ENODEV;  in chmc_probe()
709 	portid = of_getintprop_default(dp, "portid", -1);  in chmc_probe()
710 	if (portid == -1)  in chmc_probe()
713 	pval = of_get_property(dp, "memory-layout", &len);  in chmc_probe()
714 	if (pval && len > sizeof(p->layout_prop)) {  in chmc_probe()
715 		printk(KERN_ERR PFX "Unexpected memory-layout property "  in chmc_probe()
720 	err = -ENOMEM;  in chmc_probe()
727 	p->portid = portid;  in chmc_probe()
728 	p->layout_size = len;  in chmc_probe()
730 		p->layout_size = 0;  in chmc_probe()
732 		memcpy(&p->layout_prop, pval, len);  in chmc_probe()
734 	p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");  in chmc_probe()
735 	if (!p->regs) {  in chmc_probe()
740 	if (p->layout_size != 0UL) {  in chmc_probe()
741 		p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);  in chmc_probe()
742 		p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);  in chmc_probe()
743 		p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);  in chmc_probe()
744 		p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);  in chmc_probe()
745 		p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);  in chmc_probe()
750 	mc_list_add(&p->list);  in chmc_probe()
752 	printk(KERN_INFO PFX "UltraSPARC-III memory controller at %pOF [%s]\n",  in chmc_probe()
754 	       (p->layout_size ? "ACTIVE" : "INACTIVE"));  in chmc_probe()
756 	dev_set_drvdata(&op->dev, p);  in chmc_probe()
774 	return -ENODEV;  in us3mc_probe()
779 	list_del(&p->list);  in chmc_destroy()
780 	of_iounmap(&op->resource[0], p->regs, 0x48);  in chmc_destroy()
786 	mc_list_del(&p->list);  in jbusmc_destroy()
787 	of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);  in jbusmc_destroy()
793 	void *p = dev_get_drvdata(&op->dev);  in us3mc_remove()
806 		.name = "memory-controller",
834 		return -ENODEV;  in us3mc_init()