sh/kernel/disassemble.c

18 	HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7,  enumerator
69 	{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
77 	{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}},
78 	{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}},
82 	{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}},
87 	{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}},
88 	{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
89 	{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
90 	{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
91 	{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
92 	{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
93 	{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
94 	{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
95 	{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
96 	{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
97 	{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
98 	{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
99 	{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}},
100 	{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}},
101 	{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}},
102 	{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}},
103 	{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
104 	{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}},
105 	{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}},
106 	{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}},
107 	{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}},
108 	{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
109 	{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}},
110 	{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}},
111 	{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}},
112 	{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}},
114 	{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}},
117 	{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
118 	{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}},
120 	{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}},
121 	{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}},
123 	{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}},
166 	{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}},
167 	{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}},
168 	{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
169 	{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
174 	{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}},
175 	{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}},
176 	{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
177 	{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}},
178 	{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
179 	{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}},
180 	{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
181 	{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}},
182 	{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
183 	{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}},
184 	{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
185 	{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}},
191 	{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
195 	{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
196 	{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}},
197 	{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}},
198 	{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}},
199 	{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}},
200 	{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}},
201 	{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}},
202 	{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}},
208 	{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
209 	{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}},
210 	{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}},
211 	{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}},
212 	{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}},
218 	{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}},
228 	{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
237 	{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
238 	{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
279 	{"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}},