sh/kernel/disassemble.c

18 	HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7,  enumerator
68 	{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}},
69 	{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
70 	{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}},
72 	{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}},
81 	{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}},
88 	{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
89 	{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
96 	{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
103 	{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
108 	{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
113 	{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}},
117 	{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
119 	{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}},
122 	{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}},
124 	{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}},
125 	{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}},
126 	{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}},
128 	{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}},
134 	{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}},
138 	{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}},
144 	{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}},
150 	{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}},
151 	{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}},
153 	{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
157 	{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
159 	{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}},
160 	{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}},
161 	{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}},
165 	{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}},
168 	{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
169 	{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
170 	{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
171 	{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
172 	{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}},
173 	{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}},
176 	{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
178 	{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
180 	{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
182 	{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
184 	{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
186 	{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}},
187 	{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}},
188 	{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}},
189 	{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}},
190 	{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}},
191 	{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
192 	{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}},
193 	{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}},
194 	{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}},
195 	{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
203 	{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}},
204 	{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}},
205 	{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}},
206 	{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}},
207 	{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}},
208 	{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
227 	{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
228 	{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
231 	{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}},
232 	{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}},
233 	{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}},
235 	{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
236 	{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
283 	{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}},