cpu/sh4a/setup-sh7785.c

1 // SPDX-License-Identifier: GPL-2.0
18 #include <cpu/dma-register.h>
32 	.name		= "sh-sci",
53 	.name		= "sh-sci",
74 	.name		= "sh-sci",
95 	.name		= "sh-sci",
116 	.name		= "sh-sci",
137 	.name		= "sh-sci",
158 	.name		= "sh-tmu",
179 	.name		= "sh-tmu",
275 		 * vectors are 0x620-0x6c0
295 		 * vectors are 0x880-0x920
305 	.name           = "sh-dma-engine",
315 	.name		= "sh-dma-engine",
381 	SIOF, MMCIF, DU, GDTA,  enumerator
418 	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
419 	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
454 	    FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
473 	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
503 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
507 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
535 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
538 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
550 	/* disable IRQ3-0 + IRQ7-4 */  in plat_irq_setup()
553 	/* disable IRL3-0 + IRL7-4 */  in plat_irq_setup()
557 	/* select IRL mode for IRL3-0 + IRL7-4 */  in plat_irq_setup()
560 	/* disable holding function, ie enable "SH-4 Mode" */  in plat_irq_setup()
570 		/* select IRQ mode for IRL7-4 */  in plat_irq_setup_pins()
575 		/* select IRQ mode for IRL3-0 */  in plat_irq_setup_pins()
580 		/* enable IRL7-4 but don't provide any masking */  in plat_irq_setup_pins()
585 		/* enable IRL0-3 but don't provide any masking */  in plat_irq_setup_pins()
590 		/* enable IRL7-4 and mask using cpu intc controller */  in plat_irq_setup_pins()
595 		/* enable IRL0-3 and mask using cpu intc controller */  in plat_irq_setup_pins()