cpu/sh4a/setup-sh7763.c

1 // SPDX-License-Identifier: GPL-2.0
31 	.name		= "sh-sci",
52 	.name		= "sh-sci",
73 	.name		= "sh-sci",
85 		.end	= 0xffe80000 + 0x58 - 1,
96 	.name		= "sh-rtc",
97 	.id		= -1,
120 	.name		= "ohci-platform",
121 	.id		= -1,
146 	.id		= -1,
167 	.name		= "sh-tmu",
188 	.name		= "sh-tmu",
240 	RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,  enumerator
254 	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
255 	INTC_VECT(RTC, 0x4c0),
306 	    HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
317 	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
365 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
399 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
402 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
414 	/* disable IRQ7-0 */  in plat_irq_setup()
417 	/* disable IRL3-0 + IRL7-4 */  in plat_irq_setup()
428 		/* select IRQ mode for IRL3-0 + IRL7-4 */  in plat_irq_setup_pins()
433 		/* enable IRL7-4 but don't provide any masking */  in plat_irq_setup_pins()
438 		/* enable IRL0-3 but don't provide any masking */  in plat_irq_setup_pins()
443 		/* enable IRL7-4 and mask using cpu intc controller */  in plat_irq_setup_pins()
448 		/* enable IRL0-3 and mask using cpu intc controller */  in plat_irq_setup_pins()