cpu/sh4a/perf_event.c

14 #define PPC_CCBR(idx)	(0xff200800 + (sizeof(u32) * idx))
15 #define PPC_PMCTR(idx)	(0xfc100000 + (sizeof(u32) * idx))
17 #define CCBR_CIT_MASK	(0x7ff << 6)
20 #define CCBR_PPCE	(1 << 0)
37 #define PPC_PMCAT	0xfc100240
39 #define PPC_PMCAT	0xfc100080
61  *	0x0000		number of elapsed cycles
62  *	0x0200		number of elapsed cycles in privileged mode
63  *	0x0280		number of elapsed cycles while SR.BL is asserted
64  *	0x0202		instruction execution
65  *	0x0203		instruction execution in parallel
66  *	0x0204		number of unconditional branches
67  *	0x0208		number of exceptions
68  *	0x0209		number of interrupts
69  *	0x0220		UTLB miss caused by instruction fetch
70  *	0x0222		UTLB miss caused by operand access
71  *	0x02a0		number of ITLB misses
72  *	0x0028		number of accesses to instruction memories
73  *	0x0029		number of accesses to instruction cache
74  *	0x002a		instruction cache miss
75  *	0x022e		number of access to instruction X/Y memory
76  *	0x0030		number of reads to operand memories
77  *	0x0038		number of writes to operand memories
78  *	0x0031		number of operand cache read accesses
79  *	0x0039		number of operand cache write accesses
80  *	0x0032		operand cache read miss
81  *	0x003a		operand cache write miss
82  *	0x0236		number of reads to operand X/Y memory
83  *	0x023e		number of writes to operand X/Y memory
84  *	0x0237		number of reads to operand U memory
85  *	0x023f		number of writes to operand U memory
86  *	0x0337		number of U memory read buffer misses
87  *	0x02b4		number of wait cycles due to operand read access
88  *	0x02bc		number of wait cycles due to operand write access
89  *	0x0033		number of wait cycles due to operand cache read miss
90  *	0x003b		number of wait cycles due to operand cache write miss
95  * vary, but writes must always be 0.
97 #define PMCAT_EMU_CLR_MASK	((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
100 	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0000,
101 	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x0202,
102 	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0029,	/* I-cache */
103 	[PERF_COUNT_HW_CACHE_MISSES]		= 0x002a,	/* I-cache */
104 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x0204,
118 			[ C(RESULT_ACCESS) ] = 0x0031,
119 			[ C(RESULT_MISS)   ] = 0x0032,
122 			[ C(RESULT_ACCESS) ] = 0x0039,
123 			[ C(RESULT_MISS)   ] = 0x003a,
126 			[ C(RESULT_ACCESS) ] = 0,
127 			[ C(RESULT_MISS)   ] = 0,
133 			[ C(RESULT_ACCESS) ] = 0x0029,
134 			[ C(RESULT_MISS)   ] = 0x002a,
141 			[ C(RESULT_ACCESS) ] = 0,
142 			[ C(RESULT_MISS)   ] = 0,
148 			[ C(RESULT_ACCESS) ] = 0x0030,
149 			[ C(RESULT_MISS)   ] = 0,
152 			[ C(RESULT_ACCESS) ] = 0x0038,
153 			[ C(RESULT_MISS)   ] = 0,
156 			[ C(RESULT_ACCESS) ] = 0,
157 			[ C(RESULT_MISS)   ] = 0,
163 			[ C(RESULT_ACCESS) ] = 0x0222,
164 			[ C(RESULT_MISS)   ] = 0x0220,
167 			[ C(RESULT_ACCESS) ] = 0,
168 			[ C(RESULT_MISS)   ] = 0,
171 			[ C(RESULT_ACCESS) ] = 0,
172 			[ C(RESULT_MISS)   ] = 0,
178 			[ C(RESULT_ACCESS) ] = 0,
179 			[ C(RESULT_MISS)   ] = 0x02a0,
261 	for (i = 0; i < sh4a_pmu.num_events; i++)  in sh4a_pmu_disable_all()
269 	for (i = 0; i < sh4a_pmu.num_events; i++)  in sh4a_pmu_enable_all()
278 	.raw_event_mask	= 0x3ff,