Lines Matching refs:CLKDEV_CON_ID

127 	CLKDEV_CON_ID("extal", &extal_clk),
128 	CLKDEV_CON_ID("pll_clk", &pll_clk),
131 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
132 	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
133 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
134 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
135 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
136 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
146 	CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
147 	CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
148 	CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
149 	CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
150 	CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
151 	CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
152 	CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
153 	CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
160 	CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
161 	CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
162 	CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
163 	CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
164 	CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
165 	CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
166 	CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
167 	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
168 	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
169 	CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
170 	CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),