Lines Matching refs:CLKDEV_CON_ID

196 	CLKDEV_CON_ID("rclk", &r_clk),
197 	CLKDEV_CON_ID("extal", &extal_clk),
198 	CLKDEV_CON_ID("dll_clk", &dll_clk),
199 	CLKDEV_CON_ID("pll_clk", &pll_clk),
202 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
203 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
204 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
205 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
206 	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
207 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
208 	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
209 	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
210 	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
213 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216 	CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
217 	CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
218 	CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
219 	CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
220 	CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
221 	CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
222 	CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
224 	CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
225 	CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
226 	CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
230 	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
235 	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
236 	CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
237 	CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
238 	CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
239 	CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
240 	CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
241 	CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
245 	CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
246 	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
248 	CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
250 	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
252 	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
253 	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),