Lines Matching refs:CLKDEV_CON_ID

171 	CLKDEV_CON_ID("rclk", &r_clk),
172 	CLKDEV_CON_ID("extal", &extal_clk),
173 	CLKDEV_CON_ID("dll_clk", &dll_clk),
174 	CLKDEV_CON_ID("pll_clk", &pll_clk),
177 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
178 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
179 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
180 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
181 	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
182 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
183 	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
184 	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
185 	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
188 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
191 	CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
192 	CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
198 	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
205 	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
208 	CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
209 	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
212 	CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
213 	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
215 	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
216 	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),