1 // SPDX-License-Identifier: GPL-2.0
3  * Low-Level PCI Express Support for the SH7786
5  *  Copyright (C) 2009 - 2011  Paul Mundt
15 #include <linux/dma-map-ops.h>
21 #include "pcie-sh7786.h"
46 		.end	= 0xfd000000 + SZ_8M - 1,
51 		.end	= 0xc0000000 + SZ_512M - 1,
56 		.end	= 0x10000000 + SZ_64M - 1,
61 		.end	= 0xfe100000 + SZ_1M - 1,
68 		.name	= "PCIe1 MEM 0",
70 		.end	= 0xfd800000 + SZ_8M - 1,
73 		.name	= "PCIe1 MEM 1",
75 		.end	= 0xa0000000 + SZ_512M - 1,
78 		.name	= "PCIe1 MEM 2",
80 		.end	= 0x30000000 + SZ_256M - 1,
83 		.name	= "PCIe1 IO",
85 		.end	= 0xfe300000 + SZ_1M - 1,
94 		.end	= 0xfc800000 + SZ_4M - 1,
99 		.end	= 0x80000000 + SZ_512M - 1,
104 		.end	= 0x20000000 + SZ_256M - 1,
109 		.end	= 0xfcd00000 + SZ_1M - 1,
141 	if (pci_is_root_bus(dev->bus) && dev->devfn == 0) {  in sh7786_pci_fixup()
145 			r->start	= 0;  in sh7786_pci_fixup()
146 			r->end		= 0;  in sh7786_pci_fixup()
147 			r->flags	= 0;  in sh7786_pci_fixup()
158 	while (timeout--) {  in phy_wait_for_ack()
165 	return -ETIMEDOUT;  in phy_wait_for_ack()
172 	while (timeout--) {  in pci_wait_for_irq()
179 	return -ETIMEDOUT;  in pci_wait_for_irq()
205 	struct pci_channel *chan = port->hose;  in pcie_clk_init()
222 	snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index);  in pcie_clk_init()
224 	port->fclk = clk_get(NULL, fclk_name);  in pcie_clk_init()
225 	if (IS_ERR(port->fclk)) {  in pcie_clk_init()
226 		ret = PTR_ERR(port->fclk);  in pcie_clk_init()
230 	clk_enable(port->fclk);  in pcie_clk_init()
235 	clk = &port->phy_clk;  in pcie_clk_init()
239 	clk->parent = &fixed_pciexclkp;  in pcie_clk_init()
240 	clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);  in pcie_clk_init()
241 	clk->enable_bit = BITS_CKE;  in pcie_clk_init()
250 	clk_disable(port->fclk);  in pcie_clk_init()
251 	clk_put(port->fclk);  in pcie_clk_init()
260 	struct pci_channel *chan = port->hose;  in phy_init()
263 	clk_enable(&port->phy_clk);  in phy_init()
279 	clk_disable(&port->phy_clk);  in phy_init()
281 	while (timeout--) {  in phy_init()
288 	return -ETIMEDOUT;  in phy_init()
293 	struct pci_channel *chan = port->hose;  in pcie_reset()
303 	struct pci_channel *chan = port->hose;  in pcie_init()
318 	/* Initialize default capabilities. */  in pcie_init()
322 	if (port->endpoint)  in pcie_init()
330 	/* Enable data link layer active state reporting */  in pcie_init()
342 	data |= (port->index + 1) << 19;  in pcie_init()
362 	memsize = roundup_pow_of_two(memend - memstart);  in pcie_init()
370 	memsize = roundup_pow_of_two(memend - memstart);  in pcie_init()
378 		pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,  in pcie_init()
394 	pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);  in pcie_init()
435 		       port->index, (data >> 20) & 0x3f);  in pcie_init()
438 		       port->index);  in pcie_init()
440 	for (i = win = 0; i < chan->nr_resources; i++) {  in pcie_init()
441 		struct resource *res = chan->resources + i;  in pcie_init()
446 		 * We can't use the 32-bit mode windows in legacy 29-bit  in pcie_init()
449 		if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())  in pcie_init()
450 			res->flags |= IORESOURCE_DISABLED;  in pcie_init()
452 		if (res->flags & IORESOURCE_DISABLED)  in pcie_init()
462 		mask = (roundup_pow_of_two(size) / SZ_256K) - 1;  in pcie_init()
465 		pci_write_reg(chan, upper_32_bits(res->start),  in pcie_init()
467 		pci_write_reg(chan, lower_32_bits(res->start),  in pcie_init()
471 		if (res->flags & IORESOURCE_IO)  in pcie_init()
489 	dma_direct_set_offset(&pdev->dev, __pa(memory_start),  in pcibios_bus_add_device()
490 			      __pa(memory_start) - memstart, memsize);  in pcibios_bus_add_device()
508 	port->endpoint = test_mode_pin(MODE_PIN11);  in sh7786_pcie_init_hw()
516 		       port->index);  in sh7786_pcie_init_hw()
523 		       port->index);  in sh7786_pcie_init_hw()
530 			       port->index);  in sh7786_pcie_init_hw()
537 	register_pci_controller(port->hose);  in sh7786_pcie_init_hw()
555 	nr_ports = sh7786_pcie_hwops->core_init();  in sh7786_pcie_init()
559 		return -ENODEV;  in sh7786_pcie_init()
564 		return -ENOMEM;  in sh7786_pcie_init()
569 	 * This is a rather nasty hack for boards with spec-mocking FPGAs  in sh7786_pcie_init()
570 	 * that have a secondary set of clocks outside of the on-chip  in sh7786_pcie_init()
597 		port->index		= i;  in sh7786_pcie_init()
598 		port->hose		= sh7786_pci_channels + i;  in sh7786_pcie_init()
599 		port->hose->io_map_base	= port->hose->resources[0].start;  in sh7786_pcie_init()
601 		async_schedule(sh7786_pcie_hwops->port_init_hw, port);  in sh7786_pcie_init()