drivers/pci/pci-sh4.h

1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
32   #define SH4_PCIINT_MLCK	  0x00008000	/* Master Lock Error */
33   #define SH4_PCIINT_TABT	  0x00004000	/* Target Abort Error */
34   #define SH4_PCIINT_TRET	  0x00000200	/* Target Retry Error */
35   #define SH4_PCIINT_MFDE	  0x00000100	/* Master Func. Disable Error */
36   #define SH4_PCIINT_PRTY	  0x00000080	/* Address Parity Error */
37   #define SH4_PCIINT_SERR	  0x00000040	/* SERR Detection Error */
38   #define SH4_PCIINT_TWDP	  0x00000020	/* Tgt. Write Parity Error */
40   #define SH4_PCIINT_MTABT	  0x00000008	/* Master-Tgt. Abort Error */
41   #define SH4_PCIINT_MMABT	  0x00000004	/* Master-Master Abort Error */
42   #define SH4_PCIINT_MWPD	  0x00000002	/* Master Write PERR Detect */
43   #define SH4_PCIINT_MRPD	  0x00000001	/* Master Read PERR Detect */
45   #define SH4_PCIINTM_TTADIM	  BIT(14)	/* Target-target abort interrupt */
47   #define SH4_PCIINTM_MDEIM	  BIT(8)	/* Master function disable error */
48   #define SH4_PCIINTM_APEDIM	  BIT(7)	/* Address parity error detection */
50   #define SH4_PCIINTM_DPEITWM	  BIT(5)	/* Data parity error for target write */
54   #define SH4_PCIINTM_MWPDIM	  BIT(1)	/* Master write data parity error */
55   #define SH4_PCIINTM_MRDPEIM	  BIT(0)	/* Master read data parity error */
56 #define SH4_PCIALR		0x11C		/* Error Address Register */
57 #define SH4_PCICLR		0x120		/* Error Command/Data */
59   #define SH4_PCICLR_MDMA0	  0x40000000	/* DMA0 Transfer Error */
60   #define SH4_PCICLR_MDMA1	  0x20000000	/* DMA1 Transfer Error */
61   #define SH4_PCICLR_MDMA2	  0x10000000	/* DMA2 Transfer Error */
62   #define SH4_PCICLR_MDMA3	  0x08000000	/* DMA3 Transfer Error */
63   #define SH4_PCICLR_TGT	  0x04000000	/* Target Transfer Error */
64   #define SH4_PCICLR_CMDL	  0x0000000F	/* PCI Command at Error */
71   #define SH4_PCIAINT_RDPE	  0x00000002	/* Read Data Parity Error */
72   #define SH4_PCIAINT_WDPE	  0x00000001	/* Write Data Parity Error */
74 #define SH4_PCIBMLR		0x138		/* Error Bus Master Register */
75   #define SH4_PCIBMLR_REQ4	  0x00000010	/* REQ4 bus master at error */
76   #define SH4_PCIBMLR_REQ3	  0x00000008	/* REQ3 bus master at error */
77   #define SH4_PCIBMLR_REQ2	  0x00000004	/* REQ2 bus master at error */
78   #define SH4_PCIBMLR_REQ1	  0x00000002	/* REQ1 bus master at error */
79   #define SH4_PCIBMLR_REQ0	  0x00000001	/* REQ0 bus master at error */
81   #define SH4_PCIDMABT_RRBN	  0x00000001	/* DMA Arbitor Round-Robin */
123 #define SH4_PCICLKR		0x1D4		/* Clock Ctrl. Register */
124   #define SH4_PCICLKR_PCSTP	  0x00000002	/* PCI Clock Stop */
125   #define SH4_PCICLKR_BCSTP	  0x00000001	/* BCLK Clock Stop */
156 /* arch/sh/kernel/drivers/pci/ops-sh4.c */
173 	__raw_writel(val, chan->reg_base + reg);  in pci_write_reg()
179 	return __raw_readl(chan->reg_base + reg);  in pci_read_reg()