67 #define REG_W1		(MAX_BPF_JIT_REG + 1)	/* Work register 2 (odd) */  macro
71 #define REG_1		REG_W1			/* Register 1 */
102 	[REG_W1]	= 1,
592 			EMIT4(0xb9040000, REG_W1, REG_15);  in bpf_jit_prologue()
599 			EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,  in bpf_jit_prologue()
918 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
923 		EMIT2(0x1800, REG_W1, dst_reg);  in bpf_jit_insn()
935 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
940 		EMIT4(0xb9040000, REG_W1, dst_reg);  in bpf_jit_insn()
950 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
963 		EMIT2(0x1800, REG_W1, dst_reg);  in bpf_jit_insn()
985 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
996 		EMIT4(0xb9040000, REG_W1, dst_reg);  in bpf_jit_insn()
1449 		EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));  in bpf_jit_insn()
1470 		EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,  in bpf_jit_insn()
1475 		EMIT6_PCREL_RIEB(0xec000000, 0x0077, BPF_REG_3, REG_W1, 0xa,  in bpf_jit_insn()
1490 		EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);  in bpf_jit_insn()
1493 		EMIT6_PCREL_RIEC(0xec000000, 0x007f, REG_W1, MAX_TAIL_CALL_CNT - 1,  in bpf_jit_insn()
1625 			EMIT6_IMM(0xc00f0000, REG_W1, imm);  in bpf_jit_insn()
1627 			EMIT2(0x1400, REG_W1, dst_reg);  in bpf_jit_insn()
1630 			EMIT6_IMM(0xc0010000, REG_W1, imm);  in bpf_jit_insn()
1632 			EMIT4(0xb9800000, REG_W1, dst_reg);  in bpf_jit_insn()
1684 			  REG_W1, dst_reg, src_reg);  in bpf_jit_insn()