Lines Matching refs:reg_val
127 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
134 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
139 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config()
144 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config()
147 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
150 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
153 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
156 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config()
162 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
176 unsigned long i, isa_ext, reg_val; in kvm_riscv_vcpu_set_reg_config() local
181 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_config()
190 if (fls(reg_val) >= RISCV_ISA_EXT_BASE) in kvm_riscv_vcpu_set_reg_config()
197 if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) in kvm_riscv_vcpu_set_reg_config()
205 reg_val &= ~BIT(i); in kvm_riscv_vcpu_set_reg_config()
209 if (reg_val & BIT(i)) in kvm_riscv_vcpu_set_reg_config()
210 reg_val &= ~BIT(i); in kvm_riscv_vcpu_set_reg_config()
212 if (!(reg_val & BIT(i))) in kvm_riscv_vcpu_set_reg_config()
213 reg_val |= BIT(i); in kvm_riscv_vcpu_set_reg_config()
215 reg_val &= riscv_isa_extension_base(NULL); in kvm_riscv_vcpu_set_reg_config()
217 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | in kvm_riscv_vcpu_set_reg_config()
218 (reg_val & KVM_RISCV_BASE_ISA_MASK); in kvm_riscv_vcpu_set_reg_config()
219 vcpu->arch.isa[0] = reg_val; in kvm_riscv_vcpu_set_reg_config()
228 if (reg_val != riscv_cbom_block_size) in kvm_riscv_vcpu_set_reg_config()
234 if (reg_val != riscv_cboz_block_size) in kvm_riscv_vcpu_set_reg_config()
238 if (reg_val == vcpu->arch.mvendorid) in kvm_riscv_vcpu_set_reg_config()
241 vcpu->arch.mvendorid = reg_val; in kvm_riscv_vcpu_set_reg_config()
246 if (reg_val == vcpu->arch.marchid) in kvm_riscv_vcpu_set_reg_config()
249 vcpu->arch.marchid = reg_val; in kvm_riscv_vcpu_set_reg_config()
254 if (reg_val == vcpu->arch.mimpid) in kvm_riscv_vcpu_set_reg_config()
257 vcpu->arch.mimpid = reg_val; in kvm_riscv_vcpu_set_reg_config()
262 if (reg_val != (satp_mode >> SATP_MODE_SHIFT)) in kvm_riscv_vcpu_set_reg_config()
281 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_core() local
289 reg_val = cntx->sepc; in kvm_riscv_vcpu_get_reg_core()
292 reg_val = ((unsigned long *)cntx)[reg_num]; in kvm_riscv_vcpu_get_reg_core()
294 reg_val = (cntx->sstatus & SR_SPP) ? in kvm_riscv_vcpu_get_reg_core()
299 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_core()
314 unsigned long reg_val; in kvm_riscv_vcpu_set_reg_core() local
321 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_core()
325 cntx->sepc = reg_val; in kvm_riscv_vcpu_set_reg_core()
328 ((unsigned long *)cntx)[reg_num] = reg_val; in kvm_riscv_vcpu_set_reg_core()
330 if (reg_val == KVM_RISCV_MODE_S) in kvm_riscv_vcpu_set_reg_core()
361 unsigned long reg_val) in kvm_riscv_vcpu_general_set_csr() argument
369 reg_val &= VSIP_VALID_MASK; in kvm_riscv_vcpu_general_set_csr()
370 reg_val <<= VSIP_TO_HVIP_SHIFT; in kvm_riscv_vcpu_general_set_csr()
373 ((unsigned long *)csr)[reg_num] = reg_val; in kvm_riscv_vcpu_general_set_csr()
390 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_get_reg_csr() local
399 rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, ®_val); in kvm_riscv_vcpu_get_reg_csr()
402 rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val); in kvm_riscv_vcpu_get_reg_csr()
411 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_csr()
426 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_csr() local
431 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_csr()
438 rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val); in kvm_riscv_vcpu_set_reg_csr()
441 rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val); in kvm_riscv_vcpu_set_reg_csr()
455 unsigned long *reg_val) in riscv_vcpu_get_isa_ext_single() argument
467 *reg_val = 0; in riscv_vcpu_get_isa_ext_single()
469 *reg_val = 1; /* Mark the given extension as available */ in riscv_vcpu_get_isa_ext_single()
476 unsigned long reg_val) in riscv_vcpu_set_isa_ext_single() argument
488 if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa)) in riscv_vcpu_set_isa_ext_single()
496 if (reg_val == 1 && in riscv_vcpu_set_isa_ext_single()
499 else if (!reg_val && in riscv_vcpu_set_isa_ext_single()
514 unsigned long *reg_val) in riscv_vcpu_get_isa_ext_multi() argument
529 *reg_val |= KVM_REG_RISCV_ISA_MULTI_MASK(ext_id); in riscv_vcpu_get_isa_ext_multi()
537 unsigned long reg_val, bool enable) in riscv_vcpu_set_isa_ext_multi() argument
544 for_each_set_bit(i, ®_val, BITS_PER_LONG) { in riscv_vcpu_set_isa_ext_multi()
564 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_get_reg_isa_ext() local
572 reg_val = 0; in kvm_riscv_vcpu_get_reg_isa_ext()
575 rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, ®_val); in kvm_riscv_vcpu_get_reg_isa_ext()
579 rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, ®_val); in kvm_riscv_vcpu_get_reg_isa_ext()
581 reg_val = ~reg_val; in kvm_riscv_vcpu_get_reg_isa_ext()
589 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_isa_ext()
603 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_isa_ext() local
611 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_isa_ext()
616 return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val); in kvm_riscv_vcpu_set_reg_isa_ext()
618 return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true); in kvm_riscv_vcpu_set_reg_isa_ext()
620 return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false); in kvm_riscv_vcpu_set_reg_isa_ext()