115 			set_bit(host_isa, vcpu->arch.isa);  in kvm_riscv_vcpu_setup_isa()
134 		reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;  in kvm_riscv_vcpu_get_reg_config()
137 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in kvm_riscv_vcpu_get_reg_config()
142 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in kvm_riscv_vcpu_get_reg_config()
147 		reg_val = vcpu->arch.mvendorid;  in kvm_riscv_vcpu_get_reg_config()
150 		reg_val = vcpu->arch.marchid;  in kvm_riscv_vcpu_get_reg_config()
153 		reg_val = vcpu->arch.mimpid;  in kvm_riscv_vcpu_get_reg_config()
197 		if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK))  in kvm_riscv_vcpu_set_reg_config()
200 		if (!vcpu->arch.ran_atleast_once) {  in kvm_riscv_vcpu_set_reg_config()
217 			reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |  in kvm_riscv_vcpu_set_reg_config()
219 			vcpu->arch.isa[0] = reg_val;  in kvm_riscv_vcpu_set_reg_config()
226 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in kvm_riscv_vcpu_set_reg_config()
232 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in kvm_riscv_vcpu_set_reg_config()
238 		if (reg_val == vcpu->arch.mvendorid)  in kvm_riscv_vcpu_set_reg_config()
240 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
241 			vcpu->arch.mvendorid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
246 		if (reg_val == vcpu->arch.marchid)  in kvm_riscv_vcpu_set_reg_config()
248 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
249 			vcpu->arch.marchid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
254 		if (reg_val == vcpu->arch.mimpid)  in kvm_riscv_vcpu_set_reg_config()
256 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
257 			vcpu->arch.mimpid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
275 	struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in kvm_riscv_vcpu_get_reg_core()
308 	struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in kvm_riscv_vcpu_set_reg_core()
344 	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;  in kvm_riscv_vcpu_general_get_csr()
363 	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;  in kvm_riscv_vcpu_general_set_csr()
376 		WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);  in kvm_riscv_vcpu_general_set_csr()
468 	if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))  in riscv_vcpu_get_isa_ext_single()
488 	if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa))  in riscv_vcpu_set_isa_ext_single()
491 	if (!vcpu->arch.ran_atleast_once) {  in riscv_vcpu_set_isa_ext_single()
498 			set_bit(host_isa_ext, vcpu->arch.isa);  in riscv_vcpu_set_isa_ext_single()
501 			clear_bit(host_isa_ext, vcpu->arch.isa);  in riscv_vcpu_set_isa_ext_single()
643 			!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in copy_config_reg_indices()
646 			!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in copy_config_reg_indices()
697 	if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA))  in num_csr_regs()
724 	if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) {  in copy_csr_reg_indices()
769 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in num_fp_f_regs()
771 	if (riscv_isa_extension_available(vcpu->arch.isa, f))  in num_fp_f_regs()
798 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in num_fp_d_regs()
800 	if (riscv_isa_extension_available(vcpu->arch.isa, d))  in num_fp_d_regs()