Lines Matching +full:ext +full:- +full:26 +full:m
1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/alternative-macros.h>
16 #define RISCV_ISA_EXT_a ('a' - 'a')
17 #define RISCV_ISA_EXT_b ('b' - 'a')
18 #define RISCV_ISA_EXT_c ('c' - 'a')
19 #define RISCV_ISA_EXT_d ('d' - 'a')
20 #define RISCV_ISA_EXT_f ('f' - 'a')
21 #define RISCV_ISA_EXT_h ('h' - 'a')
22 #define RISCV_ISA_EXT_i ('i' - 'a')
23 #define RISCV_ISA_EXT_j ('j' - 'a')
24 #define RISCV_ISA_EXT_k ('k' - 'a')
25 #define RISCV_ISA_EXT_m ('m' - 'a')
26 #define RISCV_ISA_EXT_p ('p' - 'a')
27 #define RISCV_ISA_EXT_q ('q' - 'a')
28 #define RISCV_ISA_EXT_s ('s' - 'a')
29 #define RISCV_ISA_EXT_u ('u' - 'a')
30 #define RISCV_ISA_EXT_v ('v' - 'a')
33 * These macros represent the logical IDs of each multi-letter RISC-V ISA
35 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
42 #define RISCV_ISA_EXT_BASE 26
44 #define RISCV_ISA_EXT_SSCOFPMF 26
89 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) argument
92 #define riscv_isa_extension_available(isa_bitmap, ext) \ argument
93 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
96 riscv_has_extension_likely(const unsigned long ext) in riscv_has_extension_likely() argument
98 compiletime_assert(ext < RISCV_ISA_EXT_MAX, in riscv_has_extension_likely()
99 "ext must be < RISCV_ISA_EXT_MAX"); in riscv_has_extension_likely()
103 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) in riscv_has_extension_likely()
105 : [ext] "i" (ext) in riscv_has_extension_likely()
109 if (!__riscv_isa_extension_available(NULL, ext)) in riscv_has_extension_likely()
119 riscv_has_extension_unlikely(const unsigned long ext) in riscv_has_extension_unlikely() argument
121 compiletime_assert(ext < RISCV_ISA_EXT_MAX, in riscv_has_extension_unlikely()
122 "ext must be < RISCV_ISA_EXT_MAX"); in riscv_has_extension_unlikely()
126 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) in riscv_has_extension_unlikely()
128 : [ext] "i" (ext) in riscv_has_extension_unlikely()
132 if (__riscv_isa_extension_available(NULL, ext)) in riscv_has_extension_unlikely()
141 static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) in riscv_cpu_has_extension_likely() argument
143 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) in riscv_cpu_has_extension_likely()
146 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_likely()
149 static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext) in riscv_cpu_has_extension_unlikely() argument
151 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) in riscv_cpu_has_extension_unlikely()
154 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_unlikely()