Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
26 i-cache-block-size = <64>;
27 i-cache-sets = <64>;
28 i-cache-size = <16384>;
29 next-level-cache = <&ccache>;
33 cpu0_intc: interrupt-controller {
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
41 compatible = "sifive,u74-mc", "riscv";
43 d-cache-block-size = <64>;
44 d-cache-sets = <64>;
45 d-cache-size = <32768>;
46 d-tlb-sets = <1>;
47 d-tlb-size = <40>;
49 i-cache-block-size = <64>;
50 i-cache-sets = <64>;
51 i-cache-size = <32768>;
52 i-tlb-sets = <1>;
53 i-tlb-size = <40>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
57 tlb-split;
58 operating-points-v2 = <&cpu_opp>;
60 clock-names = "cpu";
61 #cooling-cells = <2>;
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
71 compatible = "sifive,u74-mc", "riscv";
73 d-cache-block-size = <64>;
74 d-cache-sets = <64>;
75 d-cache-size = <32768>;
76 d-tlb-sets = <1>;
77 d-tlb-size = <40>;
79 i-cache-block-size = <64>;
80 i-cache-sets = <64>;
81 i-cache-size = <32768>;
82 i-tlb-sets = <1>;
83 i-tlb-size = <40>;
84 mmu-type = "riscv,sv39";
85 next-level-cache = <&ccache>;
87 tlb-split;
88 operating-points-v2 = <&cpu_opp>;
90 clock-names = "cpu";
91 #cooling-cells = <2>;
93 cpu2_intc: interrupt-controller {
94 compatible = "riscv,cpu-intc";
95 interrupt-controller;
96 #interrupt-cells = <1>;
101 compatible = "sifive,u74-mc", "riscv";
103 d-cache-block-size = <64>;
104 d-cache-sets = <64>;
105 d-cache-size = <32768>;
106 d-tlb-sets = <1>;
107 d-tlb-size = <40>;
109 i-cache-block-size = <64>;
110 i-cache-sets = <64>;
111 i-cache-size = <32768>;
112 i-tlb-sets = <1>;
113 i-tlb-size = <40>;
114 mmu-type = "riscv,sv39";
115 next-level-cache = <&ccache>;
117 tlb-split;
118 operating-points-v2 = <&cpu_opp>;
120 clock-names = "cpu";
121 #cooling-cells = <2>;
123 cpu3_intc: interrupt-controller {
124 compatible = "riscv,cpu-intc";
125 interrupt-controller;
126 #interrupt-cells = <1>;
131 compatible = "sifive,u74-mc", "riscv";
133 d-cache-block-size = <64>;
134 d-cache-sets = <64>;
135 d-cache-size = <32768>;
136 d-tlb-sets = <1>;
137 d-tlb-size = <40>;
139 i-cache-block-size = <64>;
140 i-cache-sets = <64>;
141 i-cache-size = <32768>;
142 i-tlb-sets = <1>;
143 i-tlb-size = <40>;
144 mmu-type = "riscv,sv39";
145 next-level-cache = <&ccache>;
147 tlb-split;
148 operating-points-v2 = <&cpu_opp>;
150 clock-names = "cpu";
151 #cooling-cells = <2>;
153 cpu4_intc: interrupt-controller {
154 compatible = "riscv,cpu-intc";
155 interrupt-controller;
156 #interrupt-cells = <1>;
160 cpu-map {
185 cpu_opp: opp-table-0 {
186 compatible = "operating-points-v2";
187 opp-shared;
188 opp-375000000 {
189 opp-hz = /bits/ 64 <375000000>;
190 opp-microvolt = <800000>;
192 opp-500000000 {
193 opp-hz = /bits/ 64 <500000000>;
194 opp-microvolt = <800000>;
196 opp-750000000 {
197 opp-hz = /bits/ 64 <750000000>;
198 opp-microvolt = <800000>;
200 opp-1500000000 {
201 opp-hz = /bits/ 64 <1500000000>;
202 opp-microvolt = <1040000>;
206 thermal-zones {
207 cpu-thermal {
208 polling-delay-passive = <250>;
209 polling-delay = <15000>;
211 thermal-sensors = <&sfctemp>;
213 cooling-maps {
216 cooling-device =
242 dvp_clk: dvp-clock {
243 compatible = "fixed-clock";
244 clock-output-names = "dvp_clk";
245 #clock-cells = <0>;
247 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
248 compatible = "fixed-clock";
249 clock-output-names = "gmac0_rgmii_rxin";
250 #clock-cells = <0>;
253 gmac0_rmii_refin: gmac0-rmii-refin-clock {
254 compatible = "fixed-clock";
255 clock-output-names = "gmac0_rmii_refin";
256 #clock-cells = <0>;
259 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
260 compatible = "fixed-clock";
261 clock-output-names = "gmac1_rgmii_rxin";
262 #clock-cells = <0>;
265 gmac1_rmii_refin: gmac1-rmii-refin-clock {
266 compatible = "fixed-clock";
267 clock-output-names = "gmac1_rmii_refin";
268 #clock-cells = <0>;
271 hdmitx0_pixelclk: hdmitx0-pixel-clock {
272 compatible = "fixed-clock";
273 clock-output-names = "hdmitx0_pixelclk";
274 #clock-cells = <0>;
277 i2srx_bclk_ext: i2srx-bclk-ext-clock {
278 compatible = "fixed-clock";
279 clock-output-names = "i2srx_bclk_ext";
280 #clock-cells = <0>;
283 i2srx_lrck_ext: i2srx-lrck-ext-clock {
284 compatible = "fixed-clock";
285 clock-output-names = "i2srx_lrck_ext";
286 #clock-cells = <0>;
289 i2stx_bclk_ext: i2stx-bclk-ext-clock {
290 compatible = "fixed-clock";
291 clock-output-names = "i2stx_bclk_ext";
292 #clock-cells = <0>;
295 i2stx_lrck_ext: i2stx-lrck-ext-clock {
296 compatible = "fixed-clock";
297 clock-output-names = "i2stx_lrck_ext";
298 #clock-cells = <0>;
301 mclk_ext: mclk-ext-clock {
302 compatible = "fixed-clock";
303 clock-output-names = "mclk_ext";
304 #clock-cells = <0>;
308 compatible = "fixed-clock";
309 clock-output-names = "osc";
310 #clock-cells = <0>;
313 rtc_osc: rtc-oscillator {
314 compatible = "fixed-clock";
315 clock-output-names = "rtc_osc";
316 #clock-cells = <0>;
319 stmmac_axi_setup: stmmac-axi-config {
323 snps,blen = <256 128 64 32 0 0 0>;
326 tdm_ext: tdm-ext-clock {
327 compatible = "fixed-clock";
328 clock-output-names = "tdm_ext";
329 #clock-cells = <0>;
333 compatible = "simple-bus";
334 interrupt-parent = <&plic>;
335 #address-cells = <2>;
336 #size-cells = <2>;
340 compatible = "starfive,jh7110-clint", "sifive,clint0";
341 reg = <0x0 0x2000000 0x0 0x10000>;
342 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
349 ccache: cache-controller@2010000 {
350 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
351 reg = <0x0 0x2010000 0x0 0x4000>;
353 cache-block-size = <64>;
354 cache-level = <2>;
355 cache-sets = <2048>;
356 cache-size = <2097152>;
357 cache-unified;
360 plic: interrupt-controller@c000000 {
361 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
362 reg = <0x0 0xc000000 0x0 0x4000000>;
363 interrupts-extended = <&cpu0_intc 11>,
368 interrupt-controller;
369 #interrupt-cells = <1>;
370 #address-cells = <0>;
375 compatible = "snps,dw-apb-uart";
376 reg = <0x0 0x10000000 0x0 0x10000>;
379 clock-names = "baudclk", "apb_pclk";
382 reg-io-width = <4>;
383 reg-shift = <2>;
388 compatible = "snps,dw-apb-uart";
389 reg = <0x0 0x10010000 0x0 0x10000>;
392 clock-names = "baudclk", "apb_pclk";
395 reg-io-width = <4>;
396 reg-shift = <2>;
401 compatible = "snps,dw-apb-uart";
402 reg = <0x0 0x10020000 0x0 0x10000>;
405 clock-names = "baudclk", "apb_pclk";
408 reg-io-width = <4>;
409 reg-shift = <2>;
414 compatible = "snps,designware-i2c";
415 reg = <0x0 0x10030000 0x0 0x10000>;
417 clock-names = "ref";
420 #address-cells = <1>;
421 #size-cells = <0>;
426 compatible = "snps,designware-i2c";
427 reg = <0x0 0x10040000 0x0 0x10000>;
429 clock-names = "ref";
432 #address-cells = <1>;
433 #size-cells = <0>;
438 compatible = "snps,designware-i2c";
439 reg = <0x0 0x10050000 0x0 0x10000>;
441 clock-names = "ref";
444 #address-cells = <1>;
445 #size-cells = <0>;
451 reg = <0x0 0x10060000 0x0 0x10000>;
454 clock-names = "sspclk", "apb_pclk";
457 arm,primecell-periphid = <0x00041022>;
458 num-cs = <1>;
459 #address-cells = <1>;
460 #size-cells = <0>;
466 reg = <0x0 0x10070000 0x0 0x10000>;
469 clock-names = "sspclk", "apb_pclk";
472 arm,primecell-periphid = <0x00041022>;
473 num-cs = <1>;
474 #address-cells = <1>;
475 #size-cells = <0>;
481 reg = <0x0 0x10080000 0x0 0x10000>;
484 clock-names = "sspclk", "apb_pclk";
487 arm,primecell-periphid = <0x00041022>;
488 num-cs = <1>;
489 #address-cells = <1>;
490 #size-cells = <0>;
495 compatible = "starfive,jh7110-tdm";
496 reg = <0x0 0x10090000 0x0 0x1000>;
503 clock-names = "tdm_ahb", "tdm_apb",
510 dma-names = "rx","tx";
511 #sound-dai-cells = <0>;
516 compatible = "starfive,jh7110-usb";
517 ranges = <0x0 0x0 0x10100000 0x100000>;
518 #address-cells = <1>;
519 #size-cells = <1>;
520 starfive,stg-syscon = <&stg_syscon 0x4>;
526 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
531 reset-names = "pwrup", "apb", "axi", "utmi_apb";
534 usb_cdns3: usb@0 {
536 reg = <0x0 0x10000>,
537 <0x10000 0x10000>,
538 <0x20000 0x10000>;
539 reg-names = "otg", "xhci", "dev";
541 interrupt-names = "host", "peripheral", "otg";
543 phy-names = "cdns3,usb2-phy";
548 compatible = "starfive,jh7110-usb-phy";
549 reg = <0x0 0x10200000 0x0 0x10000>;
552 clock-names = "125m", "app_125m";
553 #phy-cells = <0>;
557 compatible = "starfive,jh7110-pcie-phy";
558 reg = <0x0 0x10210000 0x0 0x10000>;
559 #phy-cells = <0>;
563 compatible = "starfive,jh7110-pcie-phy";
564 reg = <0x0 0x10220000 0x0 0x10000>;
565 #phy-cells = <0>;
568 stgcrg: clock-controller@10230000 {
569 compatible = "starfive,jh7110-stgcrg";
570 reg = <0x0 0x10230000 0x0 0x10000>;
579 clock-names = "osc", "hifi4_core",
583 #clock-cells = <1>;
584 #reset-cells = <1>;
588 compatible = "starfive,jh7110-stg-syscon", "syscon";
589 reg = <0x0 0x10240000 0x0 0x1000>;
593 compatible = "snps,dw-apb-uart";
594 reg = <0x0 0x12000000 0x0 0x10000>;
597 clock-names = "baudclk", "apb_pclk";
600 reg-io-width = <4>;
601 reg-shift = <2>;
606 compatible = "snps,dw-apb-uart";
607 reg = <0x0 0x12010000 0x0 0x10000>;
610 clock-names = "baudclk", "apb_pclk";
613 reg-io-width = <4>;
614 reg-shift = <2>;
619 compatible = "snps,dw-apb-uart";
620 reg = <0x0 0x12020000 0x0 0x10000>;
623 clock-names = "baudclk", "apb_pclk";
626 reg-io-width = <4>;
627 reg-shift = <2>;
632 compatible = "snps,designware-i2c";
633 reg = <0x0 0x12030000 0x0 0x10000>;
635 clock-names = "ref";
638 #address-cells = <1>;
639 #size-cells = <0>;
644 compatible = "snps,designware-i2c";
645 reg = <0x0 0x12040000 0x0 0x10000>;
647 clock-names = "ref";
650 #address-cells = <1>;
651 #size-cells = <0>;
656 compatible = "snps,designware-i2c";
657 reg = <0x0 0x12050000 0x0 0x10000>;
659 clock-names = "ref";
662 #address-cells = <1>;
663 #size-cells = <0>;
668 compatible = "snps,designware-i2c";
669 reg = <0x0 0x12060000 0x0 0x10000>;
671 clock-names = "ref";
674 #address-cells = <1>;
675 #size-cells = <0>;
681 reg = <0x0 0x12070000 0x0 0x10000>;
684 clock-names = "sspclk", "apb_pclk";
687 arm,primecell-periphid = <0x00041022>;
688 num-cs = <1>;
689 #address-cells = <1>;
690 #size-cells = <0>;
696 reg = <0x0 0x12080000 0x0 0x10000>;
699 clock-names = "sspclk", "apb_pclk";
702 arm,primecell-periphid = <0x00041022>;
703 num-cs = <1>;
704 #address-cells = <1>;
705 #size-cells = <0>;
711 reg = <0x0 0x12090000 0x0 0x10000>;
714 clock-names = "sspclk", "apb_pclk";
717 arm,primecell-periphid = <0x00041022>;
718 num-cs = <1>;
719 #address-cells = <1>;
720 #size-cells = <0>;
726 reg = <0x0 0x120A0000 0x0 0x10000>;
729 clock-names = "sspclk", "apb_pclk";
732 arm,primecell-periphid = <0x00041022>;
733 num-cs = <1>;
734 #address-cells = <1>;
735 #size-cells = <0>;
739 sfctemp: temperature-sensor@120e0000 {
740 compatible = "starfive,jh7110-temp";
741 reg = <0x0 0x120e0000 0x0 0x10000>;
744 clock-names = "sense", "bus";
747 reset-names = "sense", "bus";
748 #thermal-sensor-cells = <0>;
752 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
753 reg = <0x0 0x13010000 0x0 0x10000>,
754 <0x0 0x21000000 0x0 0x400000>;
759 clock-names = "ref", "ahb", "apb";
763 reset-names = "qspi", "qspi-ocp", "rstc_ref";
764 cdns,fifo-depth = <256>;
765 cdns,fifo-width = <4>;
766 cdns,trigger-address = <0x0>;
770 syscrg: clock-controller@13020000 {
771 compatible = "starfive,jh7110-syscrg";
772 reg = <0x0 0x13020000 0x0 0x10000>;
781 clock-names = "osc", "gmac1_rmii_refin",
787 #clock-cells = <1>;
788 #reset-cells = <1>;
792 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
793 reg = <0x0 0x13030000 0x0 0x1000>;
795 pllclk: clock-controller {
796 compatible = "starfive,jh7110-pll";
798 #clock-cells = <1>;
803 compatible = "starfive,jh7110-sys-pinctrl";
804 reg = <0x0 0x13040000 0x0 0x10000>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
810 gpio-controller;
811 #gpio-cells = <2>;
815 compatible = "starfive,jh7110-wdt";
816 reg = <0x0 0x13070000 0x0 0x10000>;
819 clock-names = "apb", "core";
825 compatible = "starfive,jh7110-crypto";
826 reg = <0x0 0x16000000 0x0 0x4000>;
829 clock-names = "hclk", "ahb";
832 dmas = <&sdma 1 2>, <&sdma 0 2>;
833 dma-names = "tx", "rx";
836 sdma: dma-controller@16008000 {
838 arm,primecell-periphid = <0x00041080>;
839 reg = <0x0 0x16008000 0x0 0x4000>;
842 clock-names = "apb_pclk";
844 lli-bus-interface-ahb1;
845 mem-bus-interface-ahb1;
846 memcpy-burst-size = <256>;
847 memcpy-bus-width = <32>;
848 #dma-cells = <2>;
852 compatible = "starfive,jh7110-trng";
853 reg = <0x0 0x1600C000 0x0 0x4000>;
856 clock-names = "hclk", "ahb";
862 compatible = "starfive,jh7110-mmc";
863 reg = <0x0 0x16010000 0x0 0x10000>;
866 clock-names = "biu","ciu";
868 reset-names = "reset";
870 fifo-depth = <32>;
871 fifo-watermark-aligned;
872 data-addr = <0>;
873 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
878 compatible = "starfive,jh7110-mmc";
879 reg = <0x0 0x16020000 0x0 0x10000>;
882 clock-names = "biu","ciu";
884 reset-names = "reset";
886 fifo-depth = <32>;
887 fifo-watermark-aligned;
888 data-addr = <0>;
889 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
894 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
895 reg = <0x0 0x16030000 0x0 0x10000>;
901 clock-names = "stmmaceth", "pclk", "ptp_ref",
905 reset-names = "stmmaceth", "ahb";
907 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
908 rx-fifo-depth = <2048>;
909 tx-fifo-depth = <2048>;
910 snps,multicast-filter-bins = <64>;
911 snps,perfect-filter-entries = <256>;
912 snps,fixed-burst;
913 snps,no-pbl-x8;
915 snps,axi-config = <&stmmac_axi_setup>;
917 snps,en-tx-lpi-clockgating;
920 starfive,syscon = <&aon_syscon 0xc 0x12>;
925 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
926 reg = <0x0 0x16040000 0x0 0x10000>;
932 clock-names = "stmmaceth", "pclk", "ptp_ref",
936 reset-names = "stmmaceth", "ahb";
938 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
939 rx-fifo-depth = <2048>;
940 tx-fifo-depth = <2048>;
941 snps,multicast-filter-bins = <64>;
942 snps,perfect-filter-entries = <256>;
943 snps,fixed-burst;
944 snps,no-pbl-x8;
946 snps,axi-config = <&stmmac_axi_setup>;
948 snps,en-tx-lpi-clockgating;
951 starfive,syscon = <&sys_syscon 0x90 0x2>;
955 dma: dma-controller@16050000 {
956 compatible = "starfive,jh7110-axi-dma";
957 reg = <0x0 0x16050000 0x0 0x10000>;
960 clock-names = "core-clk", "cfgr-clk";
964 #dma-cells = <1>;
965 dma-channels = <4>;
966 snps,dma-masters = <1>;
967 snps,data-width = <3>;
968 snps,block-size = <65536 65536 65536 65536>;
969 snps,priority = <0 1 2 3>;
970 snps,axi-max-burst-len = <16>;
973 aoncrg: clock-controller@17000000 {
974 compatible = "starfive,jh7110-aoncrg";
975 reg = <0x0 0x17000000 0x0 0x10000>;
982 clock-names = "osc", "gmac0_rmii_refin",
986 #clock-cells = <1>;
987 #reset-cells = <1>;
991 compatible = "starfive,jh7110-aon-syscon", "syscon";
992 reg = <0x0 0x17010000 0x0 0x1000>;
993 #power-domain-cells = <1>;
997 compatible = "starfive,jh7110-aon-pinctrl";
998 reg = <0x0 0x17020000 0x0 0x10000>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1003 gpio-controller;
1004 #gpio-cells = <2>;
1007 pwrc: power-controller@17030000 {
1008 compatible = "starfive,jh7110-pmu";
1009 reg = <0x0 0x17030000 0x0 0x10000>;
1011 #power-domain-cells = <1>;
1014 ispcrg: clock-controller@19810000 {
1015 compatible = "starfive,jh7110-ispcrg";
1016 reg = <0x0 0x19810000 0x0 0x10000>;
1021 clock-names = "isp_top_core", "isp_top_axi",
1026 #clock-cells = <1>;
1027 #reset-cells = <1>;
1028 power-domains = <&pwrc JH7110_PD_ISP>;
1031 voutcrg: clock-controller@295c0000 {
1032 compatible = "starfive,jh7110-voutcrg";
1033 reg = <0x0 0x295c0000 0x0 0x10000>;
1040 clock-names = "vout_src", "vout_top_ahb",
1044 #clock-cells = <1>;
1045 #reset-cells = <1>;
1046 power-domains = <&pwrc JH7110_PD_VOUT>;