Lines Matching +full:cluster0 +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39";
36 tlb-split;
38 cpu0_intc: interrupt-controller {
39 compatible = "riscv,cpu-intc";
40 interrupt-controller;
41 #interrupt-cells = <1>;
46 compatible = "sifive,u74-mc", "riscv";
48 d-cache-block-size = <64>;
49 d-cache-sets = <64>;
50 d-cache-size = <32768>;
51 d-tlb-sets = <1>;
52 d-tlb-size = <32>;
54 i-cache-block-size = <64>;
55 i-cache-sets = <64>;
56 i-cache-size = <32768>;
57 i-tlb-sets = <1>;
58 i-tlb-size = <32>;
59 mmu-type = "riscv,sv39";
61 tlb-split;
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
70 cpu-map {
71 cluster0 {
83 thermal-zones {
84 cpu-thermal {
85 polling-delay-passive = <250>;
86 polling-delay = <15000>;
88 thermal-sensors = <&sfctemp>;
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
112 clock-frequency = <0>;
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
119 clock-frequency = <0>;
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
126 clock-frequency = <0>;
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
133 clock-frequency = <0>;
137 compatible = "simple-bus";
138 interrupt-parent = <&plic>;
139 #address-cells = <2>;
140 #size-cells = <2>;
144 compatible = "starfive,jh7100-clint", "sifive,clint0";
146 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
150 plic: interrupt-controller@c000000 {
151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
153 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
155 interrupt-controller;
156 #address-cells = <0>;
157 #interrupt-cells = <1>;
161 clkgen: clock-controller@11800000 {
162 compatible = "starfive,jh7100-clkgen";
165 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
166 #clock-cells = <1>;
169 rstgen: reset-controller@11840000 {
170 compatible = "starfive,jh7100-reset";
172 #reset-cells = <1>;
176 compatible = "snps,designware-i2c";
180 clock-names = "ref", "pclk";
183 #address-cells = <1>;
184 #size-cells = <0>;
189 compatible = "snps,designware-i2c";
193 clock-names = "ref", "pclk";
196 #address-cells = <1>;
197 #size-cells = <0>;
202 compatible = "starfive,jh7100-pinctrl";
205 reg-names = "gpio", "padctl";
209 gpio-controller;
210 #gpio-cells = <2>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
216 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
220 clock-names = "baudclk", "apb_pclk";
223 reg-io-width = <4>;
224 reg-shift = <2>;
229 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
233 clock-names = "baudclk", "apb_pclk";
236 reg-io-width = <4>;
237 reg-shift = <2>;
242 compatible = "snps,designware-i2c";
246 clock-names = "ref", "pclk";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "snps,designware-i2c";
259 clock-names = "ref", "pclk";
262 #address-cells = <1>;
263 #size-cells = <0>;
268 compatible = "starfive,jh7100-wdt";
272 clock-names = "apb", "core";
277 sfctemp: temperature-sensor@124a0000 {
278 compatible = "starfive,jh7100-temp";
282 clock-names = "sense", "bus";
285 reset-names = "sense", "bus";
286 #thermal-sensor-cells = <0>;