Lines Matching +full:d +full:- +full:tlb +full:- +full:sets
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
22 i-cache-size = <16384>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
31 interrupt-controller;
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
38 d-cache-sets = <64>;
39 d-cache-size = <32768>;
40 d-tlb-sets = <1>;
41 d-tlb-size = <32>;
43 i-cache-block-size = <64>;
44 i-cache-sets = <64>;
45 i-cache-size = <32768>;
46 i-tlb-sets = <1>;
47 i-tlb-size = <32>;
48 mmu-type = "riscv,sv39";
52 tlb-split;
53 next-level-cache = <&cctrllr>;
56 cpu1_intc: interrupt-controller {
57 #interrupt-cells = <1>;
58 compatible = "riscv,cpu-intc";
59 interrupt-controller;
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
68 d-tlb-sets = <1>;
69 d-tlb-size = <32>;
71 i-cache-block-size = <64>;
72 i-cache-sets = <64>;
73 i-cache-size = <32768>;
74 i-tlb-sets = <1>;
75 i-tlb-size = <32>;
76 mmu-type = "riscv,sv39";
80 tlb-split;
81 next-level-cache = <&cctrllr>;
84 cpu2_intc: interrupt-controller {
85 #interrupt-cells = <1>;
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
93 d-cache-block-size = <64>;
94 d-cache-sets = <64>;
95 d-cache-size = <32768>;
96 d-tlb-sets = <1>;
97 d-tlb-size = <32>;
99 i-cache-block-size = <64>;
100 i-cache-sets = <64>;
101 i-cache-size = <32768>;
102 i-tlb-sets = <1>;
103 i-tlb-size = <32>;
104 mmu-type = "riscv,sv39";
108 tlb-split;
109 next-level-cache = <&cctrllr>;
112 cpu3_intc: interrupt-controller {
113 #interrupt-cells = <1>;
114 compatible = "riscv,cpu-intc";
115 interrupt-controller;
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
121 d-cache-block-size = <64>;
122 d-cache-sets = <64>;
123 d-cache-size = <32768>;
124 d-tlb-sets = <1>;
125 d-tlb-size = <32>;
127 i-cache-block-size = <64>;
128 i-cache-sets = <64>;
129 i-cache-size = <32768>;
130 i-tlb-sets = <1>;
131 i-tlb-size = <32>;
132 mmu-type = "riscv,sv39";
136 tlb-split;
137 next-level-cache = <&cctrllr>;
139 cpu4_intc: interrupt-controller {
140 #interrupt-cells = <1>;
141 compatible = "riscv,cpu-intc";
142 interrupt-controller;
146 cpu-map {
172 compatible = "fixed-clock";
173 #clock-cells = <0>;
177 compatible = "microchip,mpfs-sys-controller";
182 #address-cells = <2>;
183 #size-cells = <2>;
184 compatible = "simple-bus";
187 cctrllr: cache-controller@2010000 {
188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
190 cache-block-size = <64>;
191 cache-level = <2>;
192 cache-sets = <1024>;
193 cache-size = <2097152>;
194 cache-unified;
195 interrupt-parent = <&plic>;
200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
209 plic: interrupt-controller@c000000 {
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
212 #address-cells = <0>;
213 #interrupt-cells = <1>;
214 interrupt-controller;
215 interrupts-extended = <&cpu0_intc 11>,
223 pdma: dma-controller@3000000 {
224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
226 interrupt-parent = <&plic>;
228 dma-channels = <4>;
229 #dma-cells = <1>;
233 compatible = "microchip,mpfs-clkcfg";
236 #clock-cells = <1>;
237 #reset-cells = <1>;
240 ccc_se: clock-controller@38010000 {
241 compatible = "microchip,mpfs-ccc";
244 #clock-cells = <1>;
248 ccc_ne: clock-controller@38040000 {
249 compatible = "microchip,mpfs-ccc";
252 #clock-cells = <1>;
256 ccc_nw: clock-controller@38100000 {
257 compatible = "microchip,mpfs-ccc";
260 #clock-cells = <1>;
264 ccc_sw: clock-controller@38400000 {
265 compatible = "microchip,mpfs-ccc";
268 #clock-cells = <1>;
275 reg-io-width = <4>;
276 reg-shift = <2>;
277 interrupt-parent = <&plic>;
279 current-speed = <115200>;
287 reg-io-width = <4>;
288 reg-shift = <2>;
289 interrupt-parent = <&plic>;
291 current-speed = <115200>;
299 reg-io-width = <4>;
300 reg-shift = <2>;
301 interrupt-parent = <&plic>;
303 current-speed = <115200>;
311 reg-io-width = <4>;
312 reg-shift = <2>;
313 interrupt-parent = <&plic>;
315 current-speed = <115200>;
323 reg-io-width = <4>;
324 reg-shift = <2>;
325 interrupt-parent = <&plic>;
328 current-speed = <115200>;
334 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
336 interrupt-parent = <&plic>;
339 max-frequency = <200000000>;
344 compatible = "microchip,mpfs-spi";
345 #address-cells = <1>;
346 #size-cells = <0>;
348 interrupt-parent = <&plic>;
355 compatible = "microchip,mpfs-spi";
356 #address-cells = <1>;
357 #size-cells = <0>;
359 interrupt-parent = <&plic>;
366 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
367 #address-cells = <1>;
368 #size-cells = <0>;
370 interrupt-parent = <&plic>;
377 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 interrupt-parent = <&plic>;
384 clock-frequency = <100000>;
389 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 interrupt-parent = <&plic>;
396 clock-frequency = <100000>;
401 compatible = "microchip,mpfs-can";
404 interrupt-parent = <&plic>;
410 compatible = "microchip,mpfs-can";
413 interrupt-parent = <&plic>;
419 compatible = "microchip,mpfs-macb", "cdns,macb";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 interrupt-parent = <&plic>;
425 local-mac-address = [00 00 00 00 00 00];
427 clock-names = "pclk", "hclk";
433 compatible = "microchip,mpfs-macb", "cdns,macb";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 interrupt-parent = <&plic>;
439 local-mac-address = [00 00 00 00 00 00];
441 clock-names = "pclk", "hclk";
447 compatible = "microchip,mpfs-gpio";
449 interrupt-parent = <&plic>;
450 interrupt-controller;
451 #interrupt-cells = <1>;
453 gpio-controller;
454 #gpio-cells = <2>;
459 compatible = "microchip,mpfs-gpio";
461 interrupt-parent = <&plic>;
462 interrupt-controller;
463 #interrupt-cells = <1>;
465 gpio-controller;
466 #gpio-cells = <2>;
471 compatible = "microchip,mpfs-gpio";
473 interrupt-parent = <&plic>;
474 interrupt-controller;
475 #interrupt-cells = <1>;
477 gpio-controller;
478 #gpio-cells = <2>;
483 compatible = "microchip,mpfs-rtc";
485 interrupt-parent = <&plic>;
488 clock-names = "rtc", "rtcref";
493 compatible = "microchip,mpfs-musb";
495 interrupt-parent = <&plic>;
498 interrupt-names = "dma","mc";
503 compatible = "microchip,mpfs-mailbox";
506 interrupt-parent = <&plic>;
508 #mbox-cells = <1>;