dts/microchip/mpfs-sev-kit.dts

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
13 	#address-cells = <2>;
14 	#size-cells = <2>;
15 	model = "Microchip PolarFire-SoC SEV Kit";
16 	compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
28 		stdout-path = "serial1:115200n8";
32 		timebase-frequency = <MTIMER_FREQ>;
35 	reserved-memory {
36 		#address-cells = <2>;
37 		#size-cells = <2>;
41 			compatible = "shared-dma-pool";
46 			compatible = "shared-dma-pool";
51 			compatible = "shared-dma-pool";
80 	phy-mode = "sgmii";
81 	phy-handle = <&phy0>;
82 	phy1: ethernet-phy@9 {
85 	phy0: ethernet-phy@8 {
92 	phy-mode = "sgmii";
93 	phy-handle = <&phy1>;
102 	bus-width = <4>;
103 	disable-wp;
104 	cap-sd-highspeed;
105 	cap-mmc-highspeed;
106 	mmc-ddr-1_8v;
107 	mmc-hs200-1_8v;
108 	sd-uhs-sdr12;
109 	sd-uhs-sdr25;
110 	sd-uhs-sdr50;
111 	sd-uhs-sdr104;
131 	clock-frequency = <125000000>;