powerpc/xmon/ppc-opc.c

2970 #define PPC860	PPC_OPCODE_860  macro
5221 {"mfcmpa",	XSPR(31,339,144), XSPR_MASK, PPC860,	0,		{RT}},
5222 {"mfcmpb",	XSPR(31,339,145), XSPR_MASK, PPC860,	0,		{RT}},
5223 {"mfcmpc",	XSPR(31,339,146), XSPR_MASK, PPC860,	0,		{RT}},
5224 {"mfcmpd",	XSPR(31,339,147), XSPR_MASK, PPC860,	0,		{RT}},
5225 {"mficr",	XSPR(31,339,148), XSPR_MASK, PPC860,	0,		{RT}},
5226 {"mfder",	XSPR(31,339,149), XSPR_MASK, PPC860,	0,		{RT}},
5227 {"mfcounta",	XSPR(31,339,150), XSPR_MASK, PPC860,	0,		{RT}},
5228 {"mfcountb",	XSPR(31,339,151), XSPR_MASK, PPC860,	0,		{RT}},
5229 {"mfcmpe",	XSPR(31,339,152), XSPR_MASK, PPC860,	0,		{RT}},
5230 {"mfcmpf",	XSPR(31,339,153), XSPR_MASK, PPC860,	0,		{RT}},
5231 {"mfcmpg",	XSPR(31,339,154), XSPR_MASK, PPC860,	0,		{RT}},
5232 {"mfcmph",	XSPR(31,339,155), XSPR_MASK, PPC860,	0,		{RT}},
5233 {"mflctrl1",	XSPR(31,339,156), XSPR_MASK, PPC860,	0,		{RT}},
5234 {"mflctrl2",	XSPR(31,339,157), XSPR_MASK, PPC860,	0,		{RT}},
5235 {"mfictrl",	XSPR(31,339,158), XSPR_MASK, PPC860,	0,		{RT}},
5236 {"mfbar",	XSPR(31,339,159), XSPR_MASK, PPC860,	0,		{RT}},
5296 {"mfic_cst",	XSPR(31,339,560), XSPR_MASK, PPC860,	0,		{RT}},
5297 {"mfic_adr",	XSPR(31,339,561), XSPR_MASK, PPC860,	0,		{RT}},
5298 {"mfic_dat",	XSPR(31,339,562), XSPR_MASK, PPC860,	0,		{RT}},
5299 {"mfdc_cst",	XSPR(31,339,568), XSPR_MASK, PPC860,	0,		{RT}},
5300 {"mfdc_adr",	XSPR(31,339,569), XSPR_MASK, PPC860,	0,		{RT}},
5301 {"mfdc_dat",	XSPR(31,339,570), XSPR_MASK, PPC860,	0,		{RT}},
5306 {"mfdpdr",	XSPR(31,339,630), XSPR_MASK, PPC860,	0,		{RT}},
5307 {"mfdpir",	XSPR(31,339,631), XSPR_MASK, PPC860,	0,		{RT}},
5308 {"mfimmr",	XSPR(31,339,638), XSPR_MASK, PPC860,	0,		{RT}},
5309 {"mfmi_ctr",	XSPR(31,339,784), XSPR_MASK, PPC860,	0,		{RT}},
5310 {"mfmi_ap",	XSPR(31,339,786), XSPR_MASK, PPC860,	0,		{RT}},
5311 {"mfmi_epn",	XSPR(31,339,787), XSPR_MASK, PPC860,	0,		{RT}},
5312 {"mfmi_twc",	XSPR(31,339,789), XSPR_MASK, PPC860,	0,		{RT}},
5313 {"mfmi_rpn",	XSPR(31,339,790), XSPR_MASK, PPC860,	0,		{RT}},
5314 {"mfmd_ctr",	XSPR(31,339,792), XSPR_MASK, PPC860,	0,		{RT}},
5315 {"mfm_casid",	XSPR(31,339,793), XSPR_MASK, PPC860,	0,		{RT}},
5316 {"mfmd_ap",	XSPR(31,339,794), XSPR_MASK, PPC860,	0,		{RT}},
5317 {"mfmd_epn",	XSPR(31,339,795), XSPR_MASK, PPC860,	0,		{RT}},
5318 {"mfmd_twb",	XSPR(31,339,796), XSPR_MASK, PPC860,	0,		{RT}},
5319 {"mfmd_twc",	XSPR(31,339,797), XSPR_MASK, PPC860,	0,		{RT}},
5320 {"mfmd_rpn",	XSPR(31,339,798), XSPR_MASK, PPC860,	0,		{RT}},
5321 {"mfm_tw",	XSPR(31,339,799), XSPR_MASK, PPC860,	0,		{RT}},
5322 {"mfmi_dbcam",	XSPR(31,339,816), XSPR_MASK, PPC860,	0,		{RT}},
5323 {"mfmi_dbram0",	XSPR(31,339,817), XSPR_MASK, PPC860,	0,		{RT}},
5324 {"mfmi_dbram1",	XSPR(31,339,818), XSPR_MASK, PPC860,	0,		{RT}},
5325 {"mfmd_dbcam",	XSPR(31,339,824), XSPR_MASK, PPC860,	0,		{RT}},
5326 {"mfmd_dbram0",	XSPR(31,339,825), XSPR_MASK, PPC860,	0,		{RT}},
5327 {"mfmd_dbram1",	XSPR(31,339,826), XSPR_MASK, PPC860,	0,		{RT}},
5576 {"mtcmpa",	XSPR(31,467,144), XSPR_MASK, PPC860,	0,		{RS}},
5577 {"mtcmpb",	XSPR(31,467,145), XSPR_MASK, PPC860,	0,		{RS}},
5578 {"mtcmpc",	XSPR(31,467,146), XSPR_MASK, PPC860,	0,		{RS}},
5579 {"mtcmpd",	XSPR(31,467,147), XSPR_MASK, PPC860,	0,		{RS}},
5580 {"mticr",	XSPR(31,467,148), XSPR_MASK, PPC860,	0,		{RS}},
5581 {"mtder",	XSPR(31,467,149), XSPR_MASK, PPC860,	0,		{RS}},
5582 {"mtcounta",	XSPR(31,467,150), XSPR_MASK, PPC860,	0,		{RS}},
5583 {"mtcountb",	XSPR(31,467,151), XSPR_MASK, PPC860,	0,		{RS}},
5585 {"mtcmpe",	XSPR(31,467,152), XSPR_MASK, PPC860,	0,		{RS}},
5586 {"mtcmpf",	XSPR(31,467,153), XSPR_MASK, PPC860,	0,		{RS}},
5587 {"mtcmpg",	XSPR(31,467,154), XSPR_MASK, PPC860,	0,		{RS}},
5588 {"mtcmph",	XSPR(31,467,155), XSPR_MASK, PPC860,	0,		{RS}},
5589 {"mtlctrl1",	XSPR(31,467,156), XSPR_MASK, PPC860,	0,		{RS}},
5590 {"mtlctrl2",	XSPR(31,467,157), XSPR_MASK, PPC860,	0,		{RS}},
5591 {"mtictrl",	XSPR(31,467,158), XSPR_MASK, PPC860,	0,		{RS}},
5592 {"mtbar",	XSPR(31,467,159), XSPR_MASK, PPC860,	0,		{RS}},