powerpc/xmon/ppc-opc.c

2968 #define PPC750	PPC_OPCODE_750  macro
5340 {"mfummcr0",	XSPR(31,339,936), XSPR_MASK, PPC750,	0,		{RT}},
5341 {"mfupmc1",	XSPR(31,339,937), XSPR_MASK, PPC750,	0,		{RT}},
5342 {"mfupmc2",	XSPR(31,339,938), XSPR_MASK, PPC750,	0,		{RT}},
5343 {"mfusia",	XSPR(31,339,939), XSPR_MASK, PPC750,	0,		{RT}},
5344 {"mfummcr1",	XSPR(31,339,940), XSPR_MASK, PPC750,	0,		{RT}},
5345 {"mfupmc3",	XSPR(31,339,941), XSPR_MASK, PPC750,	0,		{RT}},
5346 {"mfupmc4",	XSPR(31,339,942), XSPR_MASK, PPC750,	0,		{RT}},
5355 {"mfmmcr0",	XSPR(31,339,952), XSPR_MASK, PPC750,	0,		{RT}},
5356 {"mfpmc1",	XSPR(31,339,953), XSPR_MASK, PPC750,	0,		{RT}},
5359 {"mfpmc2",	XSPR(31,339,954), XSPR_MASK, PPC750,	0,		{RT}},
5360 {"mfsia",	XSPR(31,339,955), XSPR_MASK, PPC750,	0,		{RT}},
5362 {"mfmmcr1",	XSPR(31,339,956), XSPR_MASK, PPC750,	0,		{RT}},
5365 {"mfpmc3",	XSPR(31,339,957), XSPR_MASK, PPC750,	0,		{RT}},
5366 {"mfpmc4",	XSPR(31,339,958), XSPR_MASK, PPC750,	0,		{RT}},
5386 {"mfl2cr",	XSPR(31,339,1017), XSPR_MASK, PPC750,	0,		{RT}},
5389 {"mfictc",	XSPR(31,339,1019), XSPR_MASK, PPC750,	0,		{RT}},
5391 {"mfthrm1",	XSPR(31,339,1020), XSPR_MASK, PPC750,	0,		{RT}},
5393 {"mfthrm2",	XSPR(31,339,1021), XSPR_MASK, PPC750,	0,		{RT}},
5395 {"mfthrm3",	XSPR(31,339,1022), XSPR_MASK, PPC750,	0,		{RT}},
5660 {"mtummcr0",	XSPR(31,467,936), XSPR_MASK, PPC750,	0,		{RS}},
5661 {"mtupmc1",	XSPR(31,467,937), XSPR_MASK, PPC750,	0,		{RS}},
5662 {"mtupmc2",	XSPR(31,467,938), XSPR_MASK, PPC750,	0,		{RS}},
5663 {"mtusia",	XSPR(31,467,939), XSPR_MASK, PPC750,	0,		{RS}},
5664 {"mtummcr1",	XSPR(31,467,940), XSPR_MASK, PPC750,	0,		{RS}},
5665 {"mtupmc3",	XSPR(31,467,941), XSPR_MASK, PPC750,	0,		{RS}},
5666 {"mtupmc4",	XSPR(31,467,942), XSPR_MASK, PPC750,	0,		{RS}},
5675 {"mtmmcr0",	XSPR(31,467,952), XSPR_MASK, PPC750,	0,		{RS}},
5676 {"mtpmc1",	XSPR(31,467,953), XSPR_MASK, PPC750,	0,		{RS}},
5679 {"mtpmc2",	XSPR(31,467,954), XSPR_MASK, PPC750,	0,		{RS}},
5680 {"mtsia",	XSPR(31,467,955), XSPR_MASK, PPC750,	0,		{RS}},
5682 {"mtmmcr1",	XSPR(31,467,956), XSPR_MASK, PPC750,	0,		{RS}},
5685 {"mtpmc3",	XSPR(31,467,957), XSPR_MASK, PPC750,	0,		{RS}},
5686 {"mtpmc4",	XSPR(31,467,958), XSPR_MASK, PPC750,	0,		{RS}},
5706 {"mtl2cr",	XSPR(31,467,1017), XSPR_MASK, PPC750,	0,		{RS}},
5709 {"mtictc",	XSPR(31,467,1019), XSPR_MASK, PPC750,	0,		{RS}},
5711 {"mtthrm1",	XSPR(31,467,1020), XSPR_MASK, PPC750,	0,		{RS}},
5713 {"mtthrm2",	XSPR(31,467,1021), XSPR_MASK, PPC750,	0,		{RS}},
5715 {"mtthrm3",	XSPR(31,467,1022), XSPR_MASK, PPC750,	0,		{RS}},